JPS5884465A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPS5884465A JPS5884465A JP56182653A JP18265381A JPS5884465A JP S5884465 A JPS5884465 A JP S5884465A JP 56182653 A JP56182653 A JP 56182653A JP 18265381 A JP18265381 A JP 18265381A JP S5884465 A JPS5884465 A JP S5884465A
- Authority
- JP
- Japan
- Prior art keywords
- silicon thin
- film
- polycrystalline silicon
- thin film
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000010409 thin film Substances 0.000 claims abstract description 53
- 238000005530 etching Methods 0.000 claims abstract description 31
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims abstract description 13
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229960000583 acetic acid Drugs 0.000 claims abstract description 6
- 229910017604 nitric acid Inorganic materials 0.000 claims abstract description 6
- 239000012362 glacial acetic acid Substances 0.000 claims abstract description 5
- 238000002156 mixing Methods 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 45
- 239000011521 glass Substances 0.000 claims description 22
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 13
- 239000013078 crystal Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052710 silicon Inorganic materials 0.000 abstract description 16
- 239000010703 silicon Substances 0.000 abstract description 16
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 6
- 239000007864 aqueous solution Substances 0.000 abstract description 3
- 125000004435 hydrogen atom Chemical group [H]* 0.000 abstract description 3
- 238000002441 X-ray diffraction Methods 0.000 abstract description 2
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 2
- 239000007788 liquid Substances 0.000 abstract 2
- 229940074355 nitric acid Drugs 0.000 abstract 1
- 239000010408 film Substances 0.000 description 35
- 238000000034 method Methods 0.000 description 29
- 239000007789 gas Substances 0.000 description 27
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 17
- 229910052739 hydrogen Inorganic materials 0.000 description 16
- 239000001257 hydrogen Substances 0.000 description 16
- 230000037230 mobility Effects 0.000 description 13
- 239000000463 material Substances 0.000 description 11
- 238000010438 heat treatment Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 150000002500 ions Chemical group 0.000 description 5
- 238000000354 decomposition reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000002003 electron diffraction Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002524 electron diffraction data Methods 0.000 description 1
- 238000000921 elemental analysis Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000007733 ion plating Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000011856 silicon-based particle Substances 0.000 description 1
- 238000000527 sonication Methods 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 230000037303 wrinkles Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Weting (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は電界効果薄膜トランジスタ等Ｏ半導体素子に関
し、更に詳ＪＩＫは多結晶シリコン薄膜半導体層でその
主要部を構成した半導体素子に関する一〇である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an O semiconductor device such as a field effect thin film transistor, and more specifically JIK relates to a semiconductor device whose main part is composed of a polycrystalline silicon thin film semiconductor layer.
最近、両像読取用としてＯ１長尺化−次元７オドセンｔ
や大面積化二次元フォトセンナ等の画像ａｍ値置Ｏ走査
−路部、或いは液晶（Ｌ、Ｃと略記する）中、エレクト
ロクローζ−材料（！ｉ：Ｃと略記する）ＩＩ！いはエ
レクトール建ネツセンス材料（ＥＬと略記する）を利用
した１１ｉ＊表示デバイスの駆動回路ｓｔ１これ等の大
面積化に伴って所定の基板上に形成し九シリコン薄膜を
素材として形成することが提案されてｖｈｈ 。Recently, O1 length has been increased for double image reading - dimension 7 odocent
Image am value position O scanning-path section of large-area two-dimensional photosensor, or liquid crystal (abbreviated as L, C), electroclaw ζ-material (!i:abbreviated as C) II! A drive circuit for an 11i* display device using an elector-density material (abbreviated as EL) is proposed to be formed on a predetermined substrate using a silicon thin film as the material as these devices become larger in area. Been vhh.
斯かるシリコン薄膜は、よ〕高速化、よ）高機能化され
丸太証の画像読取装置中ｍ像＃Ｉ示義置Ｏ痰楓から、非
品質であるよｉ４多錆晶で番ることが望まれている。そ
ＯＪＩ由０１つとして上記Ｏ如ｔｏ高速、高機能の１！
堆装置ＯＳ査回路部中画像表示装置の駆動回路部を形成
すみ為の素材となるシリコン薄膜の性能を表わす値とし
て例えばＴＰＴの実効キャリア移動度（ｅｆｆｅｃｔｉ
ｖｅ ｃａｒｒｉｅｒ ｍｏｂｉｌｉｔｙ ） ＃ｅｆ
ｆとしては、大きいことが要求されるが、通常の放電分
解法で得られる非晶質シリコン薄膜に於いては精々０、
１ ｄ／ Ｖ−ｓｅａ ＠度であって、単結晶シリコン
で作成したＭＯ８ｔｊ１トランジスタに較べて蕩かに劣
り、所望の要求を満たすもので゛ないことが移１ｌｂＩ
Ｉｌが小さいことから、非晶質シリコン薄膜は薄膜作成
上の容易さと生産コストの安価を生かし切れないという
不都合さを内在している。Such a silicon thin film has become faster and more sophisticated, and the image reading device in the image reading device can detect poor quality multi-rust crystals. desired. As one of the reasons for OJI, the above is a high-speed, highly functional one!
For example, the effective carrier mobility (effecti) of TPT is a value representing the performance of the silicon thin film that is the material for forming the drive circuit section of the image display device in the OS scan circuit section of the display device.
ve carrier mobility) #ef
f is required to be large, but in amorphous silicon thin films obtained by ordinary discharge decomposition methods, it is at most 0,
1 d/V-sea @ degree, it is inferior to the MO8tj1 transistor made of single crystal silicon, and does not meet the desired requirements.
Since Il is small, amorphous silicon thin films have the disadvantage that they cannot take advantage of the ease of thin film formation and low production costs.
又、非晶質シリコンは本質的に経時変化が内在していて
単結晶に比べて劣る。Furthermore, amorphous silicon inherently suffers from changes over time and is inferior to single crystal silicon.
これに対して、多結晶シリコン薄膜は、実−スにしたと
きのその移動度μ・ｆｆが遥かに大きく、理論的には現
在得られている値よ）も、更に大きな値の移動度μｅｆ
ｆを有するものが作成され得る可能性を有している。又
、経時変化に関しても安定であることが期待される。On the other hand, polycrystalline silicon thin films have a much larger mobility μ ff when used in practice, and even a much larger mobility μ ff than the theoretical value currently available.
It is possible that something with f can be created. It is also expected to be stable with respect to changes over time.
多結晶シリコン薄ａｔ所定Ｏｊ！板上に大面積に亘って
作成する方法としては、
ＣＶ Ｄ （Ｃｈｅｍｉｃａｌ Ｖａｐｏｕｒ Ｄ＠ｐ
ｏｓｉｔｉｏｎ ）法、Ｌ Ｐ ＣＶ ｐ （Ｌｏｗ
Ｐｒｅｓｓｓｕｒｅ Ｃｈａｎｘｉｅａｌ Ｖａｐｏｕ
ｒＤ＠ｐｏｓｉｔｉｏｎ 法、 Ｍ Ｂ Ｅ （
Ｍｏ１ｅｃｕｌａｒ Ｂ＠ａｍＥｐｌｔ＊ｘ”ｌ ）
法、Ｉ Ｐ （Ｉｏｎ Ｐｌａｔｉｎｇ）法、ＧＤ（Ｇ
ｌｏｗ Ｄｉｓｃｈａｒｇｅ ）法等が知られてｉる。Polycrystalline silicon thin at specified Oj! CV D (Chemical Vapor D@p) is a method for creating a large area on a board.
position ) method, L P CV p (Low
Presssure Chanxial Vapou
rD@position method, M B E (
Mo1ecular B@amEplt＊x”l)
method, I P (Ion Plating) method, GD (G
The low discharge method and the like are known.
いずれの方法においても、基板温度はＡ＆るが、大面積
の基板の上に多結晶シリコン薄膜が作製できることが知
られている。In either method, it is known that a polycrystalline silicon thin film can be produced on a large-area substrate, although the substrate temperature is A.
しかしながら、従来、これらの方法によって作製され九
多結晶シリコン酵膜牛導体層で主要Ｓｔ構成した半導体
素子或いは半導体デバイスが所望され比特性及び信頼性
を充分発揮できないのが現状で６Δ□６
本発明は上記の点に艦み成されたものでＴｏり鋭意検討
の結果多結晶シリコン薄膜半導体層で主要部を構成した
半導体素子又は半導体デバイスの性能及び特性の安定性
Ｆｉ、（１）多結晶シリコ基いている。即ち、形成され
喪中導体層中に水素原子がある量範囲でふくまれること
、４Ｉｙ＆のエツチング液に対するエツチング速度が、
ある値以下であることが、素子特性、μｅｆｆ及び特性
の経時的な安定性を向上させ、実用上極めて優れ次使用
特性を示し、デバイスとして設計した際にも各素子の特
性上のバラツキを実質的に解消し得、実用性を飛躍的に
高めることを見出し九ものである。However, conventionally, semiconductor elements or semiconductor devices manufactured by these methods and mainly composed of a 9-polycrystalline silicon conductor layer are desired, but at present they cannot fully exhibit specific characteristics and reliability. Based on the above points, and as a result of intensive study, the stability of the performance and characteristics of a semiconductor element or semiconductor device whose main part is composed of a polycrystalline silicon thin film semiconductor layer, (1) polycrystalline silicon. It is based. That is, the formed conductor layer contains a certain amount of hydrogen atoms, and the etching rate for the etching solution of 4Iy& is as follows.
Being below a certain value improves the stability of the device characteristics, μeff, and characteristics over time, shows extremely excellent next-use characteristics in practical use, and virtually eliminates variations in the characteristics of each device when designing it as a device. Nine things have been discovered that can solve the problem and dramatically improve practicality.
本尭ａＯ目的とするところは、素子特性、μｏｆｆが従
来の多結晶シリコン薄膜中導体層で主要部を構成した半
導体素子に較べて飛躍的に向上してお９、素子特性の経
時的変化が実質的になく、極めて優れた使用特性を示す
半導体素子を提供することである。The purpose of this aO is to dramatically improve device characteristics, μoff, compared to conventional semiconductor devices whose main parts are composed of a conductor layer in a polycrystalline silicon thin film9, and to reduce changes in device characteristics over time. It is an object of the present invention to provide a semiconductor device that exhibits extremely excellent usability characteristics with substantially no oxidation.
本発明の半導体素子は３ ａｔｏｍｉｃχ′以下の水素
原子を含有し、且つ混合比が容量比で１：３：６０弗酸
（５０ｖｏｌ％水溶＊）：硝酸（ｄ＝１．ＨＩ。The semiconductor device of the present invention contains hydrogen atoms of 3 atomic χ' or less, and the mixing ratio by volume is 1:3:60 hydrofluoric acid (50 vol% water soluble*):nitric acid (d=1.HI).
６０ｖｏｌ−水溶液）：氷酢酸から成るエツチング液に
よるエツチング速度が２０ム／＠＠Ｃ以下０４Ｉ性を有
する多結晶シリコン薄膜半導体層でその主要部が構成さ
れている事を特徴とする。60 vol-aqueous solution): The etching rate with an etching solution consisting of glacial acetic acid is 20 μm/@@C or less.The main part thereof is composed of a polycrystalline silicon thin film semiconductor layer having 04I properties.
又、多結晶シリコン薄膜のＸｉｉ回折パターン又は電子
線回折パターイ（２２０）の回折強度が、全体ｏｂ薪強
度に対して３０ｓ以上、或ｉは又、多結晶シリコン薄膜
の平均結晶粒径（平均ダレインサイズ）が、２００Ａ以
上であるとされる事によシ、本ｇｉｔ、明の目的がよシ
一層効果的に達成される。In addition, the diffraction intensity of the Xii diffraction pattern or electron beam diffraction pattern (220) of the polycrystalline silicon thin film is 30 s or more with respect to the overall obstetric strength, or the average crystal grain size (average sag) of the polycrystalline silicon thin film is The purpose of this article can be more effectively achieved by setting the in-size) to 200A or more.
この様な、Ｈ含有量及び表面凹凸性を有する多結晶シリ
コン薄膜を素材として作製される半導体素子の一例とし
て０１１ｔ昇効未薄膜トランジスタ（ＦＥ−ＴＦＴ ）
は、トランジスタ４１性（ｌＩ効キャリアーモビリティ
、スレクユホールト電圧、０Ｎ１０ＦＦＢ４，１−等）
が良好となｐ１連続動作によるトランジスタ特性の経時
変化もなく、かつ素子の歩留９及び特性のパッツ命の低
下も著しく向上させることが出来る丸めにＬＣ，ＢＬ或
いはＥＣ等を利用し九表示或いはｉｉｉ＊デバイス等の
走査回路中履Ｉｍ１回路を安定して提供することが出来
る。An example of a semiconductor device manufactured using a polycrystalline silicon thin film having such H content and surface roughness is the 011t non-enhanced thin film transistor (FE-TFT).
is the transistor characteristics (I effect carrier mobility, threshold voltage, 0N10FFB4,1-, etc.)
9 display or 9 display using LC, BL, EC, etc. in rounding, which has good p1, no change in transistor characteristics over time due to continuous operation, and can significantly improve the yield of the device and the decrease in the life of the parts of the characteristics. It is possible to stably provide an Im1 circuit in a scanning circuit such as a iii* device.
本発明においては、多結晶シリコン薄膜に含有するＨ
ｔ ｔ Ｏ，０１ａｔｌ！以上にすることによって、種
々のトランジスタ骨性を向上させること７が出来る。多
結晶シリコン薄Ｊｌ［Ｋ含有されるＨｌは、主に多結晶
シリコンのグレインパクダｖ−’、ｗ存在し、５ｉ−ｎ
ｏ形でｓｉｘ子と結合している！、Ｓｉ−鵬、８１＊Ｉ
ｉ、ｏｍき結合形態のものや遊離水嵩も含んでいること
が予纏され、これ等不安定な状履で含有されている水素
に起因して、その特性の経時的変化が生じているものと
思われるが本発明者らの多くの実験事実から３ａｔ−％
以下ＯＨ量においては、トランジスタ特性の劣化％に経
時変化を起させることは、はとんどなく、上述のように
連続的にトランジスタ動作を行った場合、実効キャリア
ーモビリティの減少が見られかつ出力ドレインＩＩＩｍ
が時間とともに減少し、スレシュホールド電圧が変化す
るという経１ａｔ４１１度とするのが望ましい。In the present invention, H contained in the polycrystalline silicon thin film
t t O, 01atl! By doing the above, it is possible to improve the stiffness of various transistors. Polycrystalline silicon thin Jl [K-containing Hl mainly exists in polycrystalline silicon grain particles v-', w,
It is combined with six children in an o shape! , Si-Peng, 81*I
It is assumed that hydrogen in the i-, om-bond form or free water bulk is present, and its properties change over time due to hydrogen contained in an unstable state. However, based on the inventors' many experimental facts, 3at-%
For the following OH amounts, it is very unlikely that the deterioration percentage of transistor characteristics will change over time, and when the transistor is operated continuously as described above, a decrease in effective carrier mobility is observed and the output Drain IIIm
It is desirable that the threshold voltage decreases with time and the threshold voltage changes at 411 degrees.
本発明に於いて規定する多結晶シリコン薄膜中に含まれ
ている水素量の測定は、０．１ａｔ（ａｔｏｍｌｃ）チ
以上は通常化学分析で用いられている水素分析針（Ｐｅ
ｒｋムｎ−、Ｅｌａｈｅｒ社製Ｍｏｄｅｌ−２４０１１
１１元素分析針）により行つ九。いずれも試料は５ｍｊ
ｌ を分析針ホルダー中に装置し水嵩重量を測定し、膜
中に含まれる水嵩量を轟ｔｏｍ１ｃｍで算出した。The amount of hydrogen contained in a polycrystalline silicon thin film specified in the present invention is measured using a hydrogen analysis needle (Pe
rkmu n-, Elaher Model-24011
11 elemental analysis needle). Both samples are 5mj
1 was placed in an analytical needle holder, the bulk weight of water was measured, and the bulk amount of water contained in the membrane was calculated using a 1 cm meter.
０、 ｌ ａｔ （ａｔｏｍｉｃ）ＩＩＧ以下の微小量
分析は二次イオン質量分析計−８Ｉ ＮＳ −（Ｇａｍ
ｅｅａ ：＃に＄ＩＭｏｄｅｌ ＩＭＳ −３ｔ ）に
より行った。この分析法蒸着し、−次イオンビームのイ
オンエネルギーｔ８ＫＪＶとし、ｔｙ：ｆル＠＠ ５
Ｘ １０−”Ａ、スポットサイズ５０ＪＱＸｌ径としエ
ツチング面積紘２５０ Ｘ ２５０μｍとして、８ｉ
に対するＨイオンＯ検出強度比を求め水嵩含有量をａ
ｔｏｍ１ｅ％で算出し喪。For analysis of minute quantities below 0, l at (atomic) IIG, a secondary ion mass spectrometer-8I NS-(Gam
eea: # $IModel IMS-3t). This analytical method was used for evaporation, the ion energy of the -order ion beam was t8KJV, and ty:f @@5
x 10-"A, spot size 50JQXl diameter, etching area 250 x 250μm, 8i
Find the H ion O detection intensity ratio to the water volume content a
Mourning calculated by tom1e%.
従来多結晶シリコン薄膜は７００℃以下の低温で形成さ
れた場合には、ηりとしてμｅｆｆ、安定性など所望の
性能が連成されていなかつ喪が前記３項目水嵩量、エツ
チングレートを満足する膜であれば高性能９丁が提供可
能であることが判明し友。Conventionally, when a polycrystalline silicon thin film is formed at a low temperature of 700°C or less, the desired performance such as η, μeff, stability, etc. is not coupled, and the film satisfies the above three items of water volume and etching rate. It turned out that 9 high-performance guns could be provided.
先のｓｉｉ＊ｌＩｌ！装置や表示装置の走査回路部中部
ｌＩｈ回路部及び表示部管構成するＴＰＴ素子の半導体
層として多結晶シリコン薄Ｉ［を形成する基板材料と、
安価な＃科であるガラス、セラミックスが望ましい０本
実＠に係る多結晶質シリコン薄膜は、こＯＸ求を満良し
工業的に従来よシ切望されているＴＰＴを提供するもの
である。sii*lIl ahead! A substrate material for forming a thin polycrystalline silicon layer as a semiconductor layer of a TPT element constituting a central circuit section of a scanning circuit section and a tube of a display section of an apparatus or display device;
The polycrystalline silicon thin film, which is preferably made of inexpensive glasses and ceramics, satisfies this OX requirement and provides TPT, which has been much desired industrially.
本発明におｉて、開示されるように、特に水素化シリコ
ン化合物のガスのグロー放電分解法、為雰囲気でのシリ
コンのスパッタリング法、イオンブレーティング法、超
高真空蒸着法にお−ては、基板表面温度が５００℃以下
（約３５０〜５００℃の範囲）で本発明の目的に合致し
うる多結晶シリコン薄膜の形成が可能である０この事実
は、大面積のデバイス用の大面積にわ喪る駆ＩＩｈ回路
中走査回路の作製において、基板の均−加熱中安価な大
面積基板材料という点で有刹であるだけでなく、透過層
の表示素子用の基板中基板貴入射蓋Ｏ光電変換受元素子
の場合等ｉｉｉ像デバイスの応用において透光性のガラ
ス基板が多く値まれてお）、とＯ１！求に答えうるもの
として重要である。As disclosed in the present invention, in particular, the method of glow discharge decomposition of hydrogenated silicon compound gas, the sputtering method of silicon in an atmosphere, the ion blating method, and the ultra-high vacuum evaporation method are applicable. , it is possible to form a polycrystalline silicon thin film that meets the purpose of the present invention at a substrate surface temperature of 500°C or less (in the range of about 350 to 500°C). In the production of scanning circuits, it is not only useful in terms of inexpensive large-area substrate materials during uniform heating of the substrate; Translucent glass substrates are highly valued in applications of III-image devices such as photoelectric conversion receiving elements), and O1! This is important because it can answer the customer's needs.
従って、本発明によれば従来技術ｒＩ２ぺて、低温度領
域をも実施することが出来る為に、従来法で使用されて
いる高融点ガラス、硬ガラス等の耐熱性ガラス、耐熱性
セラミックス、ナ７アイヤ、スピネル、シリコンウェー
ハー等の伽に、一般の低融点ガラス、耐１ＩＩＩ性プク
スチックス、等も使用され得る。Therefore, according to the present invention, since it is possible to implement the conventional method in a low temperature range, it is possible to use heat-resistant glasses such as high melting point glass and hard glass, heat-resistant ceramics, and materials used in the conventional method. In addition to materials such as 7-layer glass, spinel, and silicon wafers, common low-melting glasses, 1III-resistant Puxtix, and the like may also be used.
ガラス基板としては、軟化点温度が６３０″ｏＯ並ガラ
ス、軟化点が７８０υの普通硬質ガラス、軟化点温度が
８２０’ＯＯ＊ｉ［質ガフ−Ｘ（ＪＩＳＩＭ超硬質ガラ
ス）、等が挙げられる。Examples of the glass substrate include ordinary glass with a softening point of 630''oO, ordinary hard glass with a softening point of 780υ, and Gaff-X (JISIM ultra-hard glass) with a softening point of 820'OO*i.
本発明Ｏ実施例に於いては基板ガラスとして軟化点の低
い並ガ２ス（ソーダガラス）のうち主としてコーニング
ナ７０５９ガ２スを用い友が、軟化点が１５００℃の石
英ｊラス勢を基板としても可能である◎しかし、実用上
からは、並ガ２スを用いることは安価で大面積に亘って
薄膜トランジスターを作製する上で有利である。In the embodiment of the present invention, Corning glass 7059 glass, which has a low softening point (soda glass), is mainly used as the substrate glass, while quartz glass glass, which has a softening point of 1500°C, is used as the substrate glass. However, from a practical point of view, the use of ordinary gas is advantageous in manufacturing thin film transistors over a large area at low cost.
この橡に形成される多結晶シリコン薄膜半導体層中に含
有される水嵩の量がその作成条件、作成手順、作成法に
よって種々変化するものであるが多結晶シリコン薄膜中
に含まれる水嵩量と半導体素子の一例としてのＴＦ’ｒ
（ｔ） ４Ｉ性の関係を明らかにする為、種々な作成
条件によって形成した多結晶シリ；ン薄膜中に含有され
る水嵩の量を欄定し、かつ水素量の異なるサンプルの各
々を半導体層としたＴＰＴを作成して検討し九緒果薄膜
中の水素量は３ａｔ−一〜０．０１ ｓｔ−一が善く好
ましいことが判明し良。Although the amount of water contained in the polycrystalline silicon thin film semiconductor layer formed in this cell varies depending on the preparation conditions, preparation procedure, and method, the amount of water contained in the polycrystalline silicon thin film and the semiconductor layer vary. TF'r as an example of an element
(t) In order to clarify the relationship between the 4I characteristics, the amount of water contained in polycrystalline silicon thin films formed under various production conditions was determined, and each sample with a different amount of hydrogen was compared to the semiconductor layer. A TPT was prepared and examined, and it was found that the amount of hydrogen in the Kuoguo thin film is preferably 3 at-1 to 0.01 st-1.
本発明の半導体素子の主要ｉｍｔ−構成する多結晶シリ
コン薄膜半導体層ＯＸ！１回折又は電子−回折パターン
において面指数（２２０）面からの回折強度が全ての面
指数からの回折強度（全關折強度）の３０チ以上であシ
、又、平均結晶粒径が２００Ａ以上とされることにより
、本発明の目的が一層効果的に達成される。The main imt-constituting polycrystalline silicon thin film semiconductor layer OX of the semiconductor device of the present invention! In one diffraction or electron diffraction pattern, the diffraction intensity from the (220) plane is 30 times or more of the diffraction intensity from all plane indices (total diffraction intensity), and the average crystal grain size is 200A or more. By doing so, the object of the present invention can be achieved more effectively.
本発明者等によれば多結晶質シリコン薄膜中に含有され
る水素の量は膜形成法及び膜作成条件により大幅に変る
ことが確められている。例えばシランのグロー放電によ
って膜を作成する場合には、放電パワー、圧力、基板温
度、ガス流量、Ｚラン等の原料ガスの稀釈度及び稀釈ガ
ス種などにより膜中に含まれる水素量は種々変化する。According to the present inventors, it has been confirmed that the amount of hydrogen contained in a polycrystalline silicon thin film varies greatly depending on the film formation method and film formation conditions. For example, when creating a film by glow discharge of silane, the amount of hydrogen contained in the film varies depending on the discharge power, pressure, substrate temperature, gas flow rate, dilution degree of raw material gas such as Z run, and type of diluting gas. do.
次に、多結晶シリコン薄膜のエツチング適度（エツチン
グレート）とｎτの特性との相関について詳細にＯべる
０
本発明の半導体素子の主要部を構成する多結晶シリコン
部属Ｏ評価として膜のエツチング速度は膜質や膜°Ｏ緻
書性を現わす重畳な測定量であることが本発明者等によ
って確められ良０本実ＷＡＫ於けるエツチングレートを
規定するのに用いられたエツチング液としてはシリコン
結晶の代表的エツチング液であるＯ
弗酸、硝酸、酢酸の温合ｌ１ｔ−用いた。そＯ混合ＩＩ
ハ弗＠ （５０ｖｏ １％水１１１Ｅ）、硝酸（ｄ＝
１−３８゜６０ｖｏｌチ水溶ＩＫ）、氷酢酸から構成さ
れ、それ等の組成比が１：３：６であって、ｐ ｍ ０
．３Ω・１のシリコンウェハーをエツチングし九ｌＩＯ
エツチングレートを求めると１５Ａ／ｓｅｃで６つ九（
但し、エツチング温度は２５℃）０上記の酸は、電子工
業用薬品として通常市販されてｉるもので容易に入手可
能であるＯ
多結晶シリコン薄膜のエツチングレートは膜作成条件に
より種々変ることが知られており上記エツチング縄虞淑
では１５λ／ｓｅｅ〜８０ν−・Ｃに亘って変ることが
本発明者等で確められ九〇そこでエツチングレートの異
る種々な多結晶シリコン薄膜を半導体層としてＴＰＴを
作成し、エツチングレートとの相関を調べたところ、ｎ
り特性として好ましｈｊｍのエツチングレートは２０Ａ
／ｓｅｃ以下のものであることが判明し九〇多結晶シリ
コン薄膜の結晶性には、膜作成法、膜作成条件によって
種々のものが得られることが知られている０
本発明に於いては配向性を真べる方法としてはＸ！Ｉ闘
折、鬼子線回折、で行った０作成した各多結晶シリコン
膜Ｏｘ纏回折＊＊ｔ Ｒ１ｇａｋｕ電機製Ｘ線デイフ２
クトメーター（鋼管球３５ｋＶ １０ｎｘム）によりａ
ｌｌ定し、比較を行つえ。Next, we will discuss in detail the correlation between the etching mode (etching rate) of a polycrystalline silicon thin film and the characteristics of nτ. It has been confirmed by the present inventors that is a superimposed measurement quantity that indicates the film quality and film etchability. A typical etching solution for crystals, a warm mixture of hydrofluoric acid, nitric acid, and acetic acid, was used. SOO Mixture II
Ha! (50vo 1% water 111E), nitric acid (d=
It is composed of 1-38°60 vol water-soluble IK) and glacial acetic acid, the composition ratio of which is 1:3:6, and p m 0
．． Etching a 3Ω・1 silicon wafer and producing 91IO
The etching rate is 15A/sec, which is 69 (
However, the etching temperature is 25°C) The above acid is commonly commercially available as a chemical for the electronic industry and is easily available. The etching rate of polycrystalline silicon thin films may vary depending on the film formation conditions. The present inventors have confirmed that the etching rate varies from 15λ/see to 80ν-・C in the above-mentioned etching range. When TPT was created and the correlation with etching rate was investigated, n
The preferred hjm etching rate is 20A.
It is known that various crystallinities of polycrystalline silicon thin films can be obtained depending on the film formation method and film formation conditions. X as a way to check orientation! Ox-wrapped diffraction of each polycrystalline silicon film made by I-Tori, Oniko-ray diffraction, and R1gaku Denki X-ray diffraction 2
a by a ctometer (steel tube bulb 35kV 10nx)
Determine and make comparisons.
―折角２０は２０°〜６５＠まで変化させて（１１１）
。- Change the angle of 20 from 20° to 65@ (111)
.
（２２０） ＃ （３１１） Ｏ回折ピークを検出して
その回折強度よ〉求め比ｔ−職って指標とし友０又、併
行して電子線回折強度を日本電子ｍ願黴蝿（ｎ麗−１０
０Ｕ ）の電子−回折ノ（ターンＯ回折強度Ｏ違いよシ
絖みとり、その−折強ＩＩＬＯ比を求めた。(220) # (311) Detect the O diffraction peak and use its diffraction intensity as an index. 10
The difference in the electron diffraction intensity (O) of the electron diffraction intensity (0U) was removed, and the -refraction intensity IILO ratio was determined.
ＡＳＴＭカード（Ａ ２７−１４０２ 、 ＪＣＰ戊１
９７７ ）によれば、配向の全くない多結晶シリコン薄
膜０場合回折強度の大きい面（ｂｔｋｔｊ）表示で（１
１１） ： （！２Ｇ） ： （３１１） −１００：
５５ ： ３０で、（２２０）だけＭＲ夛出してみる
と全回折強度に対する比、すなわち、
（２２０）の關Ｎ強度／（総圓折強度）は約（５５／２
５Ｇ） Ｘ １０Ｇ −２２１テＴｏ ｈ。ASTM card (A27-1402, JCP 戊1
(977), in the case of a polycrystalline silicon thin film with no orientation at all, (1
11) : (!2G) : (311) -100:
55:30, and when only (220) is extracted from the MR, the ratio to the total diffraction intensity, that is, the ratio of (220) to the total diffraction intensity is approximately (55/2).
5G)
この値を基準にして、この値の大きな配向性のいては、
経時変化が大きくなり好しくない、本発明に於いて最適
には５０チ以上が望しい〇又更に、多結鵡シリコン薄膜
ＯＨ量及表面凹凸性を満足しかつ平均結晶粒径（平均的
グレインサイズ）が大きくなるにつれてトランジスタ１
特性特に実効中ヤリアそビリティの向上することが認め
られ九〇平均的グレインサイズの値は、上述のｘ！１回
折パターンの（２２０）ピークの半値巾から通常の用い
られているＳｅｈ＠ｒｒ＠ｒ法によって求めた。平均的
グレインサイズが、２００ム以上で特に実効キャリアモ
ビリティが向上する〇特に最適には、３００Ａ以上が望
しい。Based on this value, for large orientation of this value,
In the present invention, the optimum thickness is 50 or more, which is undesirable because it increases the change over time. It is recognized that as the size of the transistor 1 becomes larger, the characteristics of the transistor 1, especially the resistance during operation, improve. It was determined from the half-width of the (220) peak of one diffraction pattern by the commonly used Seh@rr@r method. Effective carrier mobility is particularly improved when the average grain size is 200 μm or more; in particular, 300 A or more is particularly desirable.
本発明では上記し九様に３．０ＯＯＡ〜ｌμａｇ。In the present invention, 3.0OOA to 1μag as described above.
膜厚の場合には、この程１ｉｔｏ厚さでの情報が適格に
得られる。Ｘ！１回折の回折ビークＯ牛値巾より上記多
結晶イリコン薄膜のダレインナイズを求め九が、又、同
時に３０００Ａ以下Ｏ属厚Ｏ−〇については透過電子頴
黴鏡によっても調べ友。In the case of film thickness, information at a thickness of 1 ito can be adequately obtained. X! The dullness of the polycrystalline silicon thin film was determined from the width of the diffraction peak of the first diffraction, and at the same time, the thickness of the polycrystalline silicon film of less than 3000 Å was also investigated using a transmission electron microscope.
次に本発明半導体素子の一カとしてＯＴｎ Ｏ作１！プ
ロセスについて、ｊＩ１図に従ってｍｉｎする。ＴＦＴ
は牛導体層１０１、ｔＩＩＬ層１０７、オー叱ツクコン
タクト層１０３ 、１０４ 、絶縁層４０５からなる電
界効果トランジスタで、牛導体層１０１ Ｋ隣接しオー
ミンクなコンタクトが形成されて−ｌｒ、、す
るソース電極１０８ 、ドレイン電極１０１１関に電圧
を印加し、そこを流れる電流を絶縁７１１１０５を介し
て設けえゲート電極１１０にかけるバイアス電圧により
変調される（ＪＩｌｌｍの工１ｉ−に構造が示される）
ｏｆず基板１０Ｇ Ｏ洗浄を行つ先後、多結晶シリコン
薄膜１０１をその上に堆積させる〔１楊（−〕０堆積ｔ
ｉｏ＃ｍについては各実施例の所で述べる。その後オー
ミック層としてｎ（Ｐ−ｄｏｐ＠ｄシリコン）層１０２
を堆積し、ソース、ドレインをエツチングにより形成し
九（、Ｉ ＠ （ｇＵ後絶縁層１０５ｔ−その上に堆積
させる〔工Ｓ（→〕。Next, as one of the semiconductor elements of the present invention, OTnO production 1! The process is minned according to the jI1 diagram. TFT
1 is a field effect transistor consisting of a conductor layer 101, a tIIL layer 107, optical contact layers 103, 104, and an insulating layer 405, and an ohmic contact is formed adjacent to the conductor layer 101, with a source electrode -lr, . 108, a voltage is applied to the drain electrode 1011, and a current flowing therethrough is provided through the insulator 711105, and is modulated by the bias voltage applied to the gate electrode 110 (the structure is shown in JIllm, Part 1i-).
After cleaning the substrate 10G, a polycrystalline silicon thin film 101 is deposited thereon.
io#m will be described in each embodiment. After that, an n (P-dop@d silicon) layer 102 is used as an ohmic layer.
A source and a drain are formed by etching, and then an insulating layer 105t is deposited on it.
絶縁層は、Ｇの、ＬＰＧＶＤで形成されるシリコンナイ
ト２イドＳｔＯ＊ ＊ ｕ、ｏ、等の材料で構成される
０
次にソース、ドレインの電極用コンタクトホール１０６
をめけ〔工＠ （！＋ ）て、上部電極ゲート、ソース
、ドレインを配線して〔工＠ ｌｆｌ及び（４）〕完成
する０
本発明の多結晶シリコン薄膜トラ・ンジスターの安定性
を判断する経時変化の測定に関しては次のような方法に
よって行つ九。The insulating layer is made of materials such as silicon nitride StO** u, o, etc. formed by LPGVD of G. Next, contact holes 106 for source and drain electrodes are formed.
Complete [engineering @(!+)] and wiring the upper electrode gate, source, and drain. The following method is used to measure changes over time.9.
第２図に示す構造のＴＦ′Ｔを作製しゲート２０１にゲ
ート電圧、ＶＤ＝４０Ｖ、ソース２０３とドレイ７２０
２閏にドレイン電圧、ＶＤ＝４０Ｖ を印加しソース２
０３とドレイン閲に流れるドレイン電ＲＩＤをエレクト
はメーター２０８ （Ｋ＠１ｔｈｌ＠Ｆ ６１０Ｃエレ
クトロメーター）によｐｍ定しドレイン電＃ＩＯ時間的
変化を欄定した０経時変化率は、ＳＯＯ時閣Ｏ連続動作
後のドレイン電流の変動量を初期ドレイン電流で割やそ
れを１００倍し一表示で表わし丸。A TF'T having the structure shown in FIG. 2 was fabricated, the gate voltage was applied to the gate 201, VD=40V, the source 203 and the drain 720 were
Apply drain voltage, VD=40V, to source 2
03 and the drain voltage RID flowing to the drain electrode are determined as pm using meter 208 (K@1thl@F 610C electrometer), and the drain voltage #IO time change is determined as 0. The rate of change over time is 0. Divide the amount of variation in drain current after continuous operation by the initial drain current, multiply it by 100, and display it as a circle.
道りの閾値電圧は、ＭＯ８Ｆｌｉ’ｒで通常行われてい
と交差した点によって定義し九〇経時変化前と後ＯＶＴ
ＩＩの変化も同時にしらべ、変化量をダルトで表示した
０
次に本発明の実施例について述べる。The threshold voltage of the path is defined by the point where it intersects with the MO8Fli'r, which is normally done in the MO8Fli'r and the OVT before and after the aging change.
The change in II was also examined at the same time, and the amount of change was expressed in dals.Next, an embodiment of the present invention will be described.
実施例１
本実施例は、多結晶シリコン薄膜をグロー放電分解法で
Ｊ［Ｊ＝に形成し、それを用いてＴＰＴを作成し丸もの
で多結晶シリコン薄膜の形成＃ｉ第３図に示した装置を
用い友ものである。基板３００は：２− ＝ ン／ ｌ
ｊ ９ スｒｙｏｓｓ（ｏ、ｓｓｓ厚）を用い走。Example 1 In this example, a polycrystalline silicon thin film was formed to J[J= by glow discharge decomposition method, TPT was created using it, and a polycrystalline silicon thin film was formed using a round tool #i as shown in Fig. 3. It's a good idea to use the same equipment. The substrate 300 is: 2-=n/l
Run using j 9 sryoss (o, sss thickness).
先ず基［３００１−洗％ Ｌり伊１−１１／ＨＮＯ，１
０Ｈ。First, base [3001-washing% LRII1-11/HNO,1
0H.
０００Ｈの混合液でその表面を軽くエツチングし、乾燥
した後真空ペルジャー堆積室３０１内のアノード側にお
い友基板加熱ホルダー価積４５２ｍ）３０２に装着した
。The surface was lightly etched with a mixed solution of 000H, and after drying, it was mounted on a companion substrate heating holder (volume: 452 m) 302 on the anode side in a vacuum Pelger deposition chamber 301.
ソノ後ヘルジャー３０１を拡散ポンプ３０９でバックグ
ランド真空ｔＬ２．ＯＸ １０−’ Ｔｏｒｒ以下まで
排気を行表った。仁の時、この真空度が低いと反応性ガ
スが有効に菖析出に働かないばかシか膜中にＯ，Ｎが混
入し、著しく膜の抵抗を変化させるので注意を要した。After sonication, the Herjar 301 is subjected to a background vacuum tL2. using the diffusion pump 309. Evacuation was carried out to OX 10-' Torr or less. At the time of oxidation, care must be taken because if the degree of vacuum is low, the reactive gas will not work effectively for iris precipitation, and O and N will be mixed into the film, significantly changing the resistance of the film.
次にＴ、を上げて基板３００の温度をｓｏｏ”ｃに保持
した、（基板温度は熱電対３０３で監視する）。次に、
Ｈ，ガスをマス７０−コントローツー３０８で制御しな
がらペルジャー３０１内に導入して基板３００表面をク
リーニングした後、反応性気体を導入する様にし九〇基
板温度Ｔｊは３５０’Ｃに設定し九〇放電時のペルジャ
ー３０１内の圧力はＴｏｒｒＪｃ保持した。Next, T was increased to maintain the temperature of the substrate 300 at so''c (the substrate temperature is monitored with a thermocouple 303).Next,
After cleaning the surface of the substrate 300 by introducing H gas into the Pelger 301 while controlling it with the mass 70-controller 308, the reactive gas was introduced, and the substrate temperature Tj was set at 350'C. 〇The pressure inside the Pelger 301 during discharge was maintained at TorrJc.
該実施例においては、導入する反応性気体としては取扱
いの容易なＨ，ガスで３ｖｏｊｌｌＧＫ１１釈した５ｉ
Ｈ−ガス（ＳｉＨ４（３）／Ｈ！２−略記する）を用い
喪。ガス流量は５８００Ｍになるようにマ２７０−コン
トローラー３０４でコントロールして導入した０ペルジ
ヤー３０１内の圧力はペルジャー３０１の排気側の圧力
調整パルプ３１０を調節し、給体圧力計３１２を用いて
所望の圧力に設定した０ペルジヤー３０１内の圧力が安
定し九稜、カソード電極３１３に１３．５６ＭＨｚＯ高
周波電界を電源３１４によって加え、グロー放電を開始
させた。この時の電圧は０．７ＫＶ、電流は６０ｍＡ、
ＲＦ放電パワーは２０Ｗであッｆｔ。In this example, the reactive gas to be introduced is H, which is easy to handle, and 5i diluted with 3vojllGK11 gas.
Mourning using H-gas (SiH4(3)/H!2-abbreviated). The gas flow rate is controlled by the master controller 304 so that the gas flow rate is 5800M. After the pressure in the pressure gauge 301 was stabilized, a 13.56 MHzO high frequency electric field was applied to the cathode electrode 313 by the power source 314 to start glow discharge. At this time, the voltage was 0.7KV, the current was 60mA,
RF discharge power is 20W.
この条件で、放電を６０分間持続し、多結晶シリコン膜
の形成を終え、放電を中止させて原料ガスの流入も中止
させた。次に基板温度を１８０℃まで下げて保持して次
のプルセスに備え友。Under these conditions, the discharge was continued for 60 minutes, and after the formation of the polycrystalline silicon film was completed, the discharge was stopped and the inflow of the source gas was also stopped. Next, lower the board temperature to 180℃ and maintain it in preparation for the next process.
この条件下でのシリコンの膜析出速度は０．９λ／ ｓ
ｅｃであ−）九〇形成された膜の膜厚は３０００ムでそ
の均−性祉円形すング型吹き出し口を用い九場合には３
インチ×３インチの基板の大きさに対して±１０％内に
取っていた。The silicon film deposition rate under this condition is 0.9λ/s
The thickness of the film formed was 3,000 μm, and the uniformity of the film was 3,000 mm using a circular spring-shaped outlet.
It was set within ±10% with respect to the size of the board of inches x 3 inches.
又、この多結晶シリコン膜はｉ型で、抵抗値Ｆｉ〜１０
Ω・σであつた０次にこの膜を使って、第１図は示す工
１１に従・て薄膜トランジスタ（ＴＰＴ）を作成した。Moreover, this polycrystalline silicon film is of i-type and has a resistance value Fi~10
A thin film transistor (TPT) was fabricated using this zero-order film of Ω·σ according to step 11 shown in FIG.
ＴＰＴのソース・ドレインのオーミックコンタクトを良
好にせしめる丸めに基板温度は１ｓｏＣに保っ九状瞭で
ｎ＋シリ」（１００ｐｌ）ｍ ）／Ｈａと略記する）を
Ｈ２でＩ Ｑ ｖｏＪ−に稀釈され九Ｓ ｉＨａ （Ｓ
ｉＨ，（１０）／Ｈａと略記する）ガスに対して、ｍ
ｏｌ比にして５ Ｘ １０−”の割合でペルジャー３０
１内に流入させ、ペルジャー３０１内の圧力を０．１２
Ｔｏｒｒに調整してグロー放電を行ないＰのドープされ
た１層１０２ を５００人の厚さに形成した工程（ｂ
）。To make good ohmic contact between the source and drain of the TPT, the substrate temperature was kept at 1soC, and the n+ series (abbreviated as 100pl)m/Ha) was diluted to IQ voJ- with H2 and 9S. iHa (S
iH, (abbreviated as (10)/Ha) gas, m
Pelger 30 at a ratio of 5 x 10-”
1 and the pressure inside the Pelger 301 is 0.12.
The process (b
).
次にＡｊを蒸着し、その後、工１！（Ｃ）のようにフォ
トエツチングによりｈｔ及びｎ＋層１０２をソース電極
１０３の領域、ドレイン電極１０４の領域をのぞいて除
去した０次にゲート絶縁膜を形成すべくペルジャー３０
１内に再び上記の様にペルジャー３０１が排気され、基
板温度Ｔ。Next, Aj is deposited, and then step 1! As shown in (C), the HT and n+ layers 102 are removed by photoetching except for the source electrode 103 region and the drain electrode 104 region.
1, the Pelger 301 is again evacuated as described above, and the substrate temperature T is reached.
を２５０℃としてＮＨ，ガスを２０８００Ｍ、８ゑＨ４
（５ｉＨａ （１０）／Ｈｍ ）ガスを５８００Ｍ導入
してグロー放電を生起させて５ｉＮＨ５ｊ １０５を２
５０・・Ａの厚さに堆積させた０
次にフォトエツチング工程によりソース電極１０３ ド
レイン電極１０４用のコンタクトホール１０６，１，１
０６−２をあけ、その後で８ｉＮＨＭｌ ０５全面ＫＡ
ｊを蒸着して電極ＩＩ １０７を形成し喪後、ホトエツ
チング工程によりＭ電極１［１０７を加工してソース電
極用取出し電極１０８、ドレイン電極用坂出し電極１０
９及びゲート電極１１０を形成した。この後、ＨＲ雰囲
気中で２５０℃の熱処理を行った。以上の条件とプロセ
スに従って形成されたＴＰＴ（チャンネル長し＝２０μ
、チャンネル幅Ｗ＝６５０μ）は安定で良好な特性を示
し友。250℃, NH, gas 20800M, 8゜H4
(5iHa (10)/Hm) 5800M of gas is introduced to generate glow discharge and 5iNH5j 105 is 2
Contact holes 106, 1, 1 for source electrode 103 and drain electrode 104 are deposited to a thickness of 50...A.
Open 06-2, then 8iNHMl 05 full KA
After forming the electrode II 107 by vapor-depositing J, the M electrode 1 [107 is processed by a photo-etching process to form an extraction electrode 108 for the source electrode and a sloped electrode 10 for the drain electrode.
9 and a gate electrode 110 were formed. After that, heat treatment was performed at 250° C. in an HR atmosphere. TPT (channel length = 20μ) formed according to the above conditions and process
, channel width W=650μ) showed stable and good characteristics.
第４図にこの様にして試作したＴＰＴの特性例を示す。FIG. 4 shows an example of the characteristics of the TPT prototyped in this manner.
第４図にはドレイン電流工。とドレイン電圧■。の関係
をゲート電圧ＶＧをパラメータにしたＴＦＴｑＩ性例が
示されである。ゲートのスＶｙ’／ｙｘ−ル）’Ｉ圧＃
ｉ５Ｖと低くｓ Ｖｃ＝２０ＶでのＶＧ＝０の電流値の
比は３ケタ以上とれている０ＴＰＴの作成に用いた多結
晶シリコン薄膜るエツチング速度を調ぺ九結果を第１表
に示した０基板温度り社皺実施例５００℃と４５０℃４
００℃について基板温度のみ変化させ、他の条件を同じ
Ｋした場合の結果を示した０これらの多結晶シリコン薄
膜を用いて作成したＴＰＴの実効易動度（μｅｆｆ ）
も同じに表に示した０基板温度が高りＴｓ＝５００℃の
膜は膜中の水素の量が０．５ａｔ％とＩへさくてかつエ
ツチング速度が１５ム／ｓｅｅと小さく＼、この膜を用
いて作成し九ＴＰＴの５ｅｆｆは８ ｄ／ｖ、ｓｅｅで
経時変化の全くない良好な特性が得られた。Figure 4 shows the drain current. and drain voltage■. An example of TFTqI characteristics using the gate voltage VG as a parameter is shown. Gate's Vy'/yx-'I pressure#
The ratio of the current value at Vc = 20V and VG = 0 is more than 3 digits.The etching speed of the polycrystalline silicon thin film used to create TPT was investigated and the results are shown in Table 1. Substrate temperature wrinkle example 500℃ and 450℃4
The effective mobilities (μeff) of TPTs made using these polycrystalline silicon thin films are shown below, showing the results when only the substrate temperature was changed with respect to 00°C and other conditions were kept the same.
Similarly, the film shown in the table when the substrate temperature is high and Ts = 500°C has a small amount of hydrogen in the film, 0.5 at%, and a small etching rate of 15 mu/see. The 5eff of the nine TPT was 8 d/v, see, and good characteristics with no change over time were obtained.
本実施例では基板としてコーニング参７０５９ガラスを
用いたが、熱処理温度や基板温度を高くしても基板とし
て超硬質ガラスや石英ガラスを採用することにより同様
の特性を出すことができ九〇従って、本発明によれば低
温度儒よシ高温度側まで基板温度Ｔｓを広範囲内から基
板材料に従って自由に選択出来るという基板材料の選択
範囲に著しい自由度がある為に特性の優れ九ＴＰＴ蓄積
回路をよシ安価に、より簡便な装置を用いて容易に作成
することが出来る０第 １ 表
放電パワーーーーー・−・−・・・ｗｏｗＳｉＨ，ガス
１１１度−・−−−３ｖｏｊ ’ＩＧ流量（ＰＲ）−、
−・−−＝−５ＳＣＣＭ圧力（Ｐｒ） ＝−＝＝−＝＝
（ＬＯ５Ｔｏｒｒ実施例２
実施例１と同様の手ＩＮＫよって、多結晶シリ；ン膜を
グロー放電分湊の基板温［Ｔｓを４００゜４５０、５０
０℃と変化させ、 ＲＦ放電パワーＳ・Ｗ、及びシラン
ガス（８ｉＩＬ （ａ）／Ｈ＊ ）流量をｌ・８ＣＣＭ
、圧力をａ０５Ｔｏｒｒと一定にして形成したｉｌＫ
、それ係について菖ｚｌｌに示しえ。In this example, Corning Glass 7059 glass was used as the substrate, but similar characteristics can be obtained by using ultra-hard glass or quartz glass as the substrate even if the heat treatment temperature and substrate temperature are increased. According to the present invention, the substrate temperature Ts can be freely selected from a wide range according to the substrate material, from low temperature to high temperature, so that a nine-TPT storage circuit with excellent characteristics can be manufactured. It can be easily produced at a lower cost and using a simpler device.0 No. 1 Table Discharge power---wowSiH, gas 111 degrees---3voj 'IG flow rate (PR)- ,
−・−−=−5SCCM pressure (Pr) =−==−==
(LO5 Torr Example 2) Polycrystalline silicon film was heated at the substrate temperature [Ts of 400°, 450°, 50°
The temperature was changed to 0℃, and the RF discharge power S・W and the silane gas (8iIL (a)/H*) flow rate were changed to l・8CCM.
, ilK formed with a constant pressure of a05Torr
, please tell Iris about it.
第２表
放電パワー一−−−−ＳＯＷ
ＳＩＨ，ガス濃度−ｍ−・３マー−
流量（ＦＲ） −−−−−−−１１０５ｃＣ圧力
−−−−−−−−−−ａ Ｏ５Ｔｏｒｒ実施例３
１１！膣例１と同様の手順によシ、多結晶シリコン膜を
グロー放電分解の基板温度Ｔ１を４００゜４！！６．５
００℃と変化させ、放電パワー １００Ｗ及びＶ ５
：／ ｉｆ ス（８１Ｌ＜ｓ）／Ｌ ）流量を１０８０
０Ｍ、 圧力φ量、エツチング速度、及び配向性０関
係にっいてｊ１３１１に示した。Table 2 Discharge power ----SOW SIH, gas concentration -m・3mer- Flow rate (FR)---1105cC pressure
----------a O5Torr Example 3 11! Following the same procedure as Example 1, the substrate temperature T1 for glow discharge decomposition of the polycrystalline silicon film was set to 400°4! ! 6.5
00℃, discharge power 100W and V 5
:/if s(81L<s)/L) flow rate to 1080
The relationship between 0M, pressure φ amount, etching rate, and orientation 0 is shown in j1311.
第 ｓｌ！ｌｌ！
上記のトランジスタの４を性は、基板温度がＳＯＯ℃の
場合（試料４３−ｓ ） ｓ、ｆｆ＝ｈｓで経時変化の
ない良好な特性てあっ九。No. sl! ll! Characteristic 4 of the above transistor has good characteristics with no change over time when the substrate temperature is SOO°C (sample 43-s) s, ff = hs.
実施例４
実施例１と同様に準備された同等のコーニングガラス基
＠ ＷＯＯをペルジャー３０１内の上部アノード側の基
板加熱ホルダー３０２に密着して同定し、下部カソード
３１３の電極板上に基板と対向するように多結晶シリコ
ン板（図示しない：５ＵＮＳ）を静置し良。ペルジャー
３０１を拡散ポンプ３０９で真空状態とし、！Ｘ１０Ｔ
ｏｒｒ まで排気し、基板加熱ホルダーｓｏ２を加熱し
て基板謝の表面温度を４５０℃に保った。続いて高Ｍｆ
ｌｔガスをマス７０−メーター３０８ Ｋよってａｓ８
ｃｃＭペルジャー内に導入し、更Ｋ Ａｒ／Ｈｅ （容
量比で５ｅｅｓ比）混合ガｘを−ｒ ｘ ７ ａ −７
ｆ −ｆｉ −３０７ＫよってｉｏｓｃｃＭの流量でペ
ルジャー３０１内に導入し、メインパルプ３１Ｇを絞っ
てペルジャー内圧をａＯ！１Ｔｏｒｒに設定し良。Example 4 An equivalent Corning glass substrate @WOO prepared in the same manner as in Example 1 was identified by closely contacting the substrate heating holder 302 on the upper anode side in the Pelger 301, and placed on the electrode plate of the lower cathode 313 facing the substrate. Place the polycrystalline silicon plate (not shown: 5UNS) as it is. Put the Pelger 301 into a vacuum state with the diffusion pump 309, and! X10T
The temperature of the surface of the substrate was maintained at 450° C. by heating the substrate heating holder SO2. Next, high Mf
lt gas mass 70-meter 308 K therefore as8
Introduced into a ccM Pel jar and added K Ar/He (5ees ratio by volume) mixed gas x -r x 7 a -7
Therefore, f -fi -307K is introduced into the Pel jar 301 at a flow rate of iosccM, and the main pulp 31G is squeezed to reduce the Pel jar internal pressure to aO! It is good to set it to 1 Torr.
ペルジャー内圧が安定してから、下部カソード電極３１
３にＩ Ｌ ５８ ＭＨｚの高周波電源３１４によによ
って、１．５ＶＫ印加してカッー寮ケの結晶シリコン板
とアノード（基板加熱ホルダー）３０！間にグ四−放電
を生起させ九。ＲＦ放電パワー（°進行波−反射波）は
１２Ｇであった。この条件でシリコン膜の成長速度はａ
２λ／ｗ、であ〕、４時間成長させて約α３μ膜を形成
しえ。After the Pelger internal pressure stabilizes, the lower cathode electrode 31
3, a 58 MHz high frequency power supply 314 is used to apply 1.5 VK to the crystal silicon plate and anode (substrate heating holder) 30! During this time, a discharge is generated. The RF discharge power (° traveling wave−reflected wave) was 12G. Under these conditions, the growth rate of the silicon film is a
2λ/w], and was grown for 4 hours to form an approximately α3μ film.
シリコン層中に含有する。Ｈ量はａＳ、エツチング速度
は１９ム／寓であった。Contained in the silicon layer. The amount of H was aS, and the etching rate was 19 mm/mm.
続いて実施例１と同様の工＠（４−〜−）ＫよってＴＰ
Ｔを作製した。この素子の実効モビリｆｉｏｏ時間テＩ
ＤＲａ１％以下、Ｖｔｈは全く不変であ〉、経時のＤＣ
動作特性は良好であった。Subsequently, the same process as in Example 1 is carried out by TP
I made T. The effective mobility time of this element
DRa is 1% or less, Vth is completely unchanged〉, and DC over time
The operating characteristics were good.
実施例５
実施例１と同様に準備されたコーニング７ｏ５９ガラス
基板ＳＯＯをＺＸＩＯＴｅｒｒまで減圧される超高真空
槽５０１内の基板ホルダーｓ０２に装填し真空槽内の圧
力が５Ｘ１０ Ｔｏｒｒ以下の圧力にまで減圧した後
、タンタルヒーターＳＯ８Ｋより基せ、発射する電子ビ
ームをシリコン蒸発体４０ｚＫｉｌｌ射させ、シリコン
蒸発体を蒸発させ、つづいてシャッター５０７を開き、
基板ＳＯＯに膜厚ａＳμ厚になるよう水晶振動子膜厚計
ＳＯ６でコントルールし、多結晶シリコン膜を形成しえ
。このときの蒸着中の圧力＋６１ Ｘ １０ Ｔｅｒｒ
、蒸着達度紘Ｌ４人／−であつ九（試料Ａ６ｓ−１）。Example 5 A Corning 7o59 glass substrate SOO prepared in the same manner as in Example 1 was loaded into the substrate holder s02 in the ultra-high vacuum chamber 501, which was depressurized to ZXIO Terra, and the pressure in the vacuum chamber was depressurized to 5×10 Torr or less. After that, an electron beam is emitted from the tantalum heater SO8K to evaporate the silicon evaporator 40zKill, and then the shutter 507 is opened.
A polycrystalline silicon film is formed on the substrate SOO by controlling it with a crystal resonator film thickness gauge SO6 so that the film thickness is aSμ. Pressure during vapor deposition at this time +61 x 10 Terr
, the vapor deposition level was 4/- and 9 (sample A6s-1).
他方、洗滌し九コーニング７ｏ５９ガ２ス基板を再び基
板ホルダー５０２ Ｋ ｍ！定し、真空槽ｓｏｉ内の圧
力が８Ｘ１０ Ｔｅｒｒ以下の圧力まで減圧し先後、
高純度水素ガス（ｅｔｓｉｎ＊１） をバリアプルリ
ークバルブ５０ｇにより真空槽内に導入し、曽ｉ５．ｏ
１内圧力を５Ｘ １０ ”Ｔｏｒｒ Ｋ設定しえ。基
板温度リプン薄膜を形成した（試料Ａｓ−ｚ）。On the other hand, wash the 9 Corning 7o59 gas board and put it back into the board holder 502 Km! After setting the pressure in the vacuum tank soi to 8×10 Terr or less,
High-purity hydrogen gas (ETSIN*1) was introduced into the vacuum chamber through a 50g barrier pull leak valve, and then the i5. o
The internal pressure was set at 5×10” Torr K. A thin film was formed at a substrate temperature (sample As-z).
試料４５−１．４５−２ Ｋ−’）いて各ｋＯ水嵩量。Sample 45-1.45-2 K-') and each kO water volume.
エツチング速度、配向性、及び実施例１と同様のプロセ
スによって作成し九ＴＰＴの実効移動変声ｏｆｆを表４
に示した。Table 4 shows the etching speed, orientation, and effective transfer tone off of nine TPTs prepared by the same process as in Example 1.
It was shown to.
第４表
表４かられかるように試料Ａ＄−１，５−２ともにエツ
チング速度、配向性ａｆｔｆｆ同一値を示し良好で６つ
え。実効移動度（μ＊ｔｔ’） ＃ｉ１桁以上試料／％
５−２は試料ｍ５−１に比べ大きく、ＴＦＴ用の半導
体層として試料４５−２ｔ）薄膜の方がよ）好ましいこ
とが判った。Table 4 As can be seen from Table 4, both samples A$-1 and A$-5-2 had the same values for etching rate and orientation aftff, which was good. Effective mobility (μ*tt') #i 1 digit or more sample/%
5-2 was larger than sample m5-1, and it was found that sample 45-2t) thin film was more preferable as a semiconductor layer for TFT.
実施例６
本実ＢＡ第６図に示すイオンブレーティング堆積装置を
用いて多結晶シリコン薄膜を作製し、腋薄膜を素材とし
て薄膜トランジスターを作製し先例を以下に述べる。Example 6 A polycrystalline silicon thin film was produced using the ion blasting deposition apparatus shown in FIG. 6 of the present BA, and a thin film transistor was produced using the axillary thin film as a material.The example will be described below.
初めに減圧しうる堆積＠ ６０３内Ｋ ｗｏｎ−ｄ＠Ｐ
＊多結晶シリコンのシリコン蒸発体６０６をボード２０
７内に置き、コーニングφ７０！！９基板を支持体に設
置し、堆積室内をペースプレッシャーが約ｌＸｌ０ Ｔ
ｏｒｒ に表るまで排気し九毅、ガス導入管５０５を通
じて純度９９．９９９ ＊ ＯＨｔガスを水素分圧Ｐ８
がＩＸＩ（ｒ’ＴｏｒｒＫなる様にして堆積室内に導入
し九。使用したガス導入管ＳＯＳは内径２■で、先のル
ープ状の部分にガス吹惠出し口が＝口間隔てａ５ｍの孔
が開いているものを使用し九。Deposition that can be depressurized first @ 603 Kwon-d@P
*Silicone evaporator 606 of polycrystalline silicon is connected to board 20
Place it in 7, Corning φ70! ! 9 substrates were placed on the support, and the pace pressure in the deposition chamber was approximately lXl0T.
99.999 * OHt gas with a purity of 99.999 through the gas introduction pipe 505 to a hydrogen partial pressure of P8.
IXI (r'TorrK) was introduced into the deposition chamber.The gas inlet pipe SOS used had an inner diameter of 2 mm, and the loop-shaped part at the end had a gas outlet with holes spaced a5 m apart. Use the one that is open.
次に、高周波コイル６１０ （直径５−）に１１ｓ６Ｍ
Ｊ１ｘの高周波を印加して、出力を１００Ｗに設定して
、コイル内部分に高周波ブ２ズ！雰囲気を形成した。Next, add 11s6M to the high frequency coil 610 (diameter 5-).
Apply J1x high frequency, set the output to 100W, and apply high frequency buzz to the inside of the coil! It created an atmosphere.
他方、支持体６１１−１ 、６１１−２は回転させなが
ら、加熱装置６１２を動作状態にして約４７５℃に加熱
しておいた。On the other hand, while rotating the supports 611-1 and 611-2, the heating device 612 was turned on and heated to about 475°C.
次に、蒸発体６０６にエレク）ａ７ガン６０８より照射
し、加熱したシリコン粒子を飛翔させた。Next, the evaporator 606 was irradiated with an electric A7 gun 608 to cause the heated silicon particles to fly.
このときのエレクトロンガンのパワーハ約αＳＶであっ
た。The power of the electron gun at this time was approximately αSV.
この様にして５０分間で５０００ムの多結晶シリコン薄
膜が形成された。In this manner, a polycrystalline silicon thin film of 5,000 μm was formed in 50 minutes.
この薄膜を用いて前記の実施例と同様なプロセスで薄膜
トランジスターを作製した。下ｌ！に本実施例における
膜中に含まれる水素量及び膜のエツチング速度、薄膜ト
ランジスタの実効移動度を示した。同時に、水素分圧が
４Ｘ１０ Ｔｏｒｒの場合と水素を導入しないで膜を形
成した場合についてのデータも示し丸。Using this thin film, a thin film transistor was fabricated using the same process as in the previous example. Down! 2 shows the amount of hydrogen contained in the film, the etching rate of the film, and the effective mobility of the thin film transistor in this example. At the same time, data for the case where the hydrogen partial pressure was 4X10 Torr and the case where the film was formed without introducing hydrogen are also shown.
第 ５ 表
ＰＨ，＝ Ｉ Ｘ １０ Ｔｏｒｒの水素分圧で膜を形
成し九トランジスタでは、ドレイン電圧Ｖ。、ゲート電
圧光を４０Ｖで連続印加後の電流変化（経時変化）が全
くなく、移動度もｚ４と大きく良好なトランジスタ特性
を示した。それに対し水素量の多い場合は経時変化が大
きく、水素の少ない場合は移動度が小さくいという結果
を得た。Table 5 For nine transistors with a film formed at a hydrogen partial pressure of PH, = I x 10 Torr, the drain voltage V. There was no current change (change over time) after continuous application of gate voltage light of 40 V, and the mobility was z4, showing good transistor characteristics. On the other hand, when the amount of hydrogen is large, the change over time is large, and when the amount of hydrogen is small, the mobility is small.
第１図は、本発明の半導体素子を作製する丸めの工程を
説明する模式的工程図、第２図は本発明の半導体素子の
特性を測定する為の回路を模式的に示し九説明図、第３
因、第５図、第６図紘各々本発明に係わる半導体膜作製
装置の例を説明する為の模式的説明図、第４図は本発明
の半導体、素子のＶ、−ＩＤ特性の一例を示す説明図で
ある。
１０Ｇ−基板 １０１−半導体層１０２・・
・電極層 １０５−絶縁層出願人 中ヤノン株
式会社
第５置FIG. 1 is a schematic process diagram illustrating the rounding process for manufacturing the semiconductor device of the present invention, and FIG. 2 is an explanatory diagram schematically showing a circuit for measuring the characteristics of the semiconductor device of the present invention. Third
Incidentally, FIGS. 5 and 6 are schematic explanatory diagrams for explaining an example of the semiconductor film manufacturing apparatus according to the present invention, and FIG. 4 shows an example of the V and -ID characteristics of the semiconductor and element of the present invention. FIG. 10G-substrate 101-semiconductor layer 102...
・Electrode layer 105-Insulating layer Applicant Nakayanon Co., Ltd. No. 5
Claims (2)
、且つ混合比が容量比で１ ： ｓ ： ｒｓｏ弗駿（
５０ｖｏｌ−水＄Ｉり：耐硝酸 ｄ＝１．３８ 、６０
ｖｏｌｌ！水濤筐）：氷酢酸から成るエツチングＩＩＫ
よるエツチング適度が２ＯＡ”／ｓ＠ｅ以下の特性を有
する多結晶シリコン薄膜半導体層でその主要部が構成さ
れている事１＊黴とする半導体素子。(1) Contains 3 atomic or less O water atoms, and the mixing ratio is 1 : s : rso 弗Shun (
50vol-water $I: Nitric acid resistance d=1.38, 60
vol! Etching IIK consisting of glacial acetic acid
1. A semiconductor device whose main part is constituted by a polycrystalline silicon thin film semiconductor layer having an etching rate of 2OA"/s@e or less.
は電子ｍ回折パターンによ！ （，１２Ｇ） ＯＩＩ折
強＊０食回折強度に対する割合が３０１以上である譬許
請求ＯＳＳ第１項に記載Ｏ半導体素子０ 。 （２） 前記半導体層の平均鐘晶ｆｌＬｇＩｋが２００
ム０以上である特許請筆０１１１１Ｊｌｘ項に記載の半
導体素子。 （優 前記半導体層がガラスａ基１ＩＩＬに形成されで
ある特許−求Ｏ＠８１１１１．１項にｌｉ！載の半導体
素子。(2) Based on the semiconductor layer oxmrxtIIt pattern or electron m diffraction pattern! (, 12G) O semiconductor element 0 according to claim OSS item 1, in which the ratio of OII diffraction intensity to 0 eclipse diffraction intensity is 301 or more. (2) The average bell crystal flLgIk of the semiconductor layer is 200
The semiconductor device according to patent application no. (Excellent) A semiconductor device as described in [email protected], in which the semiconductor layer is formed on a glass a-based substrate.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56182653A JPS5884465A (en) | 1981-11-13 | 1981-11-13 | Semiconductor element |
| DE19823241959 DE3241959A1 (en) | 1981-11-13 | 1982-11-12 | Semiconductor component |
| US07/188,677 US4905072A (en) | 1981-11-13 | 1988-04-29 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56182653A JPS5884465A (en) | 1981-11-13 | 1981-11-13 | Semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5884465A true JPS5884465A (en) | 1983-05-20 |
| JPH021366B2 JPH021366B2 (en) | 1990-01-11 |
Family
ID=16122071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56182653A Granted JPS5884465A (en) | 1981-11-13 | 1981-11-13 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5884465A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6066825A (en) * | 1983-09-22 | 1985-04-17 | Toshiba Corp | Manufacture of semiconductor device |
| US7154147B1 (en) | 1990-11-26 | 2006-12-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| US8106867B2 (en) | 1990-11-26 | 2012-01-31 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5511329A (en) * | 1978-07-08 | 1980-01-26 | Shunpei Yamazaki | Semiconductor device |
| JPS5550663A (en) * | 1978-10-07 | 1980-04-12 | Shunpei Yamazaki | Semiconductor device and method of fabricating the same |
| JPS55151329A (en) * | 1979-05-14 | 1980-11-25 | Shunpei Yamazaki | Fabricating method of semiconductor device |
| JPS55154726A (en) * | 1979-05-22 | 1980-12-02 | Shunpei Yamazaki | Manufacture of semiconductor device |
| JPS56138929A (en) * | 1980-03-31 | 1981-10-29 | Canon Inc | Component solution for etching |
| JPH021365A (en) * | 1988-06-09 | 1990-01-05 | Honshu Paper Co Ltd | Thermal recording material |
| JPH021367A (en) * | 1988-06-09 | 1990-01-05 | Fuji Photo Film Co Ltd | Thermal recording material |
-
1981
- 1981-11-13 JP JP56182653A patent/JPS5884465A/en active Granted
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5511329A (en) * | 1978-07-08 | 1980-01-26 | Shunpei Yamazaki | Semiconductor device |
| JPS5550663A (en) * | 1978-10-07 | 1980-04-12 | Shunpei Yamazaki | Semiconductor device and method of fabricating the same |
| JPS55151329A (en) * | 1979-05-14 | 1980-11-25 | Shunpei Yamazaki | Fabricating method of semiconductor device |
| JPS55154726A (en) * | 1979-05-22 | 1980-12-02 | Shunpei Yamazaki | Manufacture of semiconductor device |
| JPS56138929A (en) * | 1980-03-31 | 1981-10-29 | Canon Inc | Component solution for etching |
| JPH021365A (en) * | 1988-06-09 | 1990-01-05 | Honshu Paper Co Ltd | Thermal recording material |
| JPH021367A (en) * | 1988-06-09 | 1990-01-05 | Fuji Photo Film Co Ltd | Thermal recording material |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6066825A (en) * | 1983-09-22 | 1985-04-17 | Toshiba Corp | Manufacture of semiconductor device |
| JPH0324778B2 (en) * | 1983-09-22 | 1991-04-04 | Tokyo Shibaura Electric Co | |
| US7154147B1 (en) | 1990-11-26 | 2006-12-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| US7423290B2 (en) | 1990-11-26 | 2008-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| US8026886B2 (en) | 1990-11-26 | 2011-09-27 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| US8106867B2 (en) | 1990-11-26 | 2012-01-31 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH021366B2 (en) | 1990-01-11 |
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