JPS5871214U - Muting signal generation circuit - Google Patents
Muting signal generation circuitInfo
- Publication number
- JPS5871214U JPS5871214U JP16505381U JP16505381U JPS5871214U JP S5871214 U JPS5871214 U JP S5871214U JP 16505381 U JP16505381 U JP 16505381U JP 16505381 U JP16505381 U JP 16505381U JP S5871214 U JPS5871214 U JP S5871214U
- Authority
- JP
- Japan
- Prior art keywords
- turned
- potential
- power
- muting signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
- Noise Elimination (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のミューティング信号発生回路を示す回路
図、第2図はその特性図、第3図は本考案の一実施例を
示す回路図、第4図はその特性図、及び第5図は減電圧
特性を説明する為の特性図である。
主な図番の説明、9・・・電圧検出回路、13゜17・
・・定電流回路、22・・・ダイオード。Fig. 1 is a circuit diagram showing a conventional muting signal generation circuit, Fig. 2 is a characteristic diagram thereof, Fig. 3 is a circuit diagram showing an embodiment of the present invention, Fig. 4 is a characteristic diagram thereof, and Fig. 5 is a circuit diagram showing a conventional muting signal generation circuit. The figure is a characteristic diagram for explaining the voltage reduction characteristics. Explanation of main drawing numbers, 9...Voltage detection circuit, 13°17.
... Constant current circuit, 22... Diode.
Claims (1)
ング信号を発生する回路であって、電源投入時に直ちに
第1の所定電位となる第1点の電位と、電源投入後所定
の時間を経過した後第1の所定電位よりも大なる第2の
所定電位となる第2点の電位とを比較して、電源投入か
ら一定時間が経過する迄の間、オン状態を保つトランジ
スタを含む電圧検出回路と、前記第1点の電位を安定に
保つ為の第1の定電流回路と、前記第2点の電位を安定
に保つ為の第2の定電流回路と、前記電圧検出回路の状
態に応じてミューティング信号を出力する出力端子と、
前記電圧検出回路と出力端子との間に挿入され、電源電
圧が低下した時オフとなる定電圧素子とから成るミュー
ティング信号発生回路。This is a circuit that generates a muting signal to prevent the generation of a shock sound when the power is turned on, and has a potential at a first point that becomes a first predetermined potential immediately when the power is turned on, and a muting signal that is set to a first predetermined potential when the power is turned on, and when a predetermined time has passed after the power is turned on. a voltage detection circuit including a transistor that maintains an on state for a certain period of time after power is turned on by comparing the potential at a second point with a second predetermined potential that is greater than the first predetermined potential; , a first constant current circuit for keeping the potential at the first point stable, a second constant current circuit for keeping the potential at the second point stable, and depending on the state of the voltage detection circuit. an output terminal that outputs a muting signal;
A muting signal generation circuit comprising a constant voltage element inserted between the voltage detection circuit and the output terminal and turned off when the power supply voltage drops.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16505381U JPS5871214U (en) | 1981-11-04 | 1981-11-04 | Muting signal generation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16505381U JPS5871214U (en) | 1981-11-04 | 1981-11-04 | Muting signal generation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5871214U true JPS5871214U (en) | 1983-05-14 |
JPS6349934Y2 JPS6349934Y2 (en) | 1988-12-22 |
Family
ID=29957262
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16505381U Granted JPS5871214U (en) | 1981-11-04 | 1981-11-04 | Muting signal generation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5871214U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006245817A (en) * | 2005-03-01 | 2006-09-14 | Nec Corp | Power amplifier |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5529844U (en) * | 1978-08-16 | 1980-02-26 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5323787A (en) * | 1976-08-13 | 1978-03-04 | Intaa Patsuku Kk | Device for automatically wrapping cylindrical product by shrinkage |
-
1981
- 1981-11-04 JP JP16505381U patent/JPS5871214U/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5529844U (en) * | 1978-08-16 | 1980-02-26 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006245817A (en) * | 2005-03-01 | 2006-09-14 | Nec Corp | Power amplifier |
JP4650026B2 (en) * | 2005-03-01 | 2011-03-16 | 日本電気株式会社 | Power amplifier |
Also Published As
Publication number | Publication date |
---|---|
JPS6349934Y2 (en) | 1988-12-22 |
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