JPS5826718U - Tape recorder muting circuit - Google Patents
Tape recorder muting circuitInfo
- Publication number
- JPS5826718U JPS5826718U JP11899181U JP11899181U JPS5826718U JP S5826718 U JPS5826718 U JP S5826718U JP 11899181 U JP11899181 U JP 11899181U JP 11899181 U JP11899181 U JP 11899181U JP S5826718 U JPS5826718 U JP S5826718U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- muting
- ground
- base
- tape recorder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図示した回路は、本考案のミューティング回路の一実施
例である。
主な図番の説明、４・・・・・・主増幅回路、５・・・
・・・出力端子、６・・・・・・ミューティング用トラ
ンジスター、７・・・・・・信号伝送路、１０・・・・
・・制御トランジスター、１３・・・・・・ブリッジ回
路、１９・・・・・・検出用トランジスター、２１・・
・・・・ミューティング信号発生回路。The illustrated circuit is one embodiment of the muting circuit of the present invention. Explanation of main drawing numbers, 4... Main amplifier circuit, 5...
... Output terminal, 6 ... Muting transistor, 7 ... Signal transmission line, 10 ...
...Control transistor, 13...Bridge circuit, 19...Detection transistor, 21...
...Muting signal generation circuit.
Claims (1)
ているミューティング用トランジスターと、該ミューテ
ィング用トランジスターの動作を制御するべく接続され
ていると共にオン状態にあるとき前記ミューティング用
トランジスターをオン状態にせしめる制御トランジスタ
ーと、電源線路と接地間に接続されていると共に４つの
抵抗より成るブリッジ回路と、該ブリッジ回路の平衡端
子にエミッタ及びベースが接続されていると共にコレク
タが前記制御トランジスターのベースに接続されている
検出用トランジスターと、該検出用トランジスターのベ
ースと接地間に接続された第１コンデンサーと、電源供
給状態において常時充電されていると共に電源遮断時前
記制御トランジスターを所定時間オン状態にせしめる電
流を供給する第２コンデンサーとより成るテープレコー
ダーのミューティング回路。A muting transistor whose collector-emitter path is connected between the signal transmission path and ground, and a muting transistor that is connected to control the operation of the muting transistor and turns on the muting transistor when it is in the on state. a bridge circuit connected between a power supply line and ground and consisting of four resistors; an emitter and a base connected to the balanced terminals of the bridge circuit, and a collector connected to the base of the control transistor; a first capacitor connected between the base of the detection transistor and ground; and a first capacitor connected between the base of the detection transistor and ground, which are constantly charged in a power supply state and keep the control transistor in an on state for a predetermined time when the power is cut off. A muting circuit for a tape recorder comprising a second capacitor for supplying a current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11899181U JPS5826718U (en) | 1981-08-10 | 1981-08-10 | Tape recorder muting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11899181U JPS5826718U (en) | 1981-08-10 | 1981-08-10 | Tape recorder muting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5826718U true JPS5826718U (en) | 1983-02-21 |
| JPS634290Y2 JPS634290Y2 (en) | 1988-02-03 |
Family
ID=29913081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11899181U Granted JPS5826718U (en) | 1981-08-10 | 1981-08-10 | Tape recorder muting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5826718U (en) |
-
1981
- 1981-08-10 JP JP11899181U patent/JPS5826718U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS634290Y2 (en) | 1988-02-03 |
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