JPS585824A - Data transferring system between channels - Google Patents
Data transferring system between channelsInfo
- Publication number
- JPS585824A JPS585824A JP10398181A JP10398181A JPS585824A JP S585824 A JPS585824 A JP S585824A JP 10398181 A JP10398181 A JP 10398181A JP 10398181 A JP10398181 A JP 10398181A JP S585824 A JPS585824 A JP S585824A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- data
- bus
- register
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
Description
【発明の詳細な説明】
本楯明は共通バスに中央処理装置Ｃ以下ＣＰＵと称す）
、主記憶装置（以下ＭＭと称す）、チャネル装置ｃ以下
チャネルと称す）′ｖｔＩＩ続した計算機システムにお
いて、チャネル間で直接データ転送するようにしｆｃ％
のでＴｏ４゜
第１１！１！ｌｌＫ示すようなこの種のシステムは既に
公知であり、一般ＫＣＰＵ又はチャネルＣＨＯ〜ＣＨ２
が共通パスＣ−Ｂ、ＵＳの支配権を獲得してパスマスク
となり、メモリＭＭ５１他のチャネルをバススレーブ゛
として指定してデータ転送やコマンド転送を行なうｔの
である。尚、バス支配権の獲得ア゛ルゴリズ＾等につい
ては、４１Ｍ８８５２−１１！１！４１等種々提案され
ているのでここでは省略する。[Detailed description of the invention] This shield uses a common bus as a central processing unit (hereinafter referred to as CPU)
, main memory (hereinafter referred to as MM), channel device (hereinafter referred to as channel)'vtII, data is transferred directly between channels in a connected computer system fc%
So To4゜No.11!1! This kind of system as shown in 1K is already known, and the general KCPU or channels CHO to CH2
acquires control over the common paths CB and US, becomes a path mask, and specifies the memory MM51 and other channels as bus slaves to perform data transfer and command transfer. It should be noted that various algorithms such as 41M8852-11!1!41 have been proposed for obtaining bus control rights, so a description thereof will be omitted here.
従来のシステムではＣＰＵＭ ＭＭ、ＣＰＵ←→ＣＨ，
及びＣＨ４４ＭＭ間のデータ転送に可能であるがＣＨ＋
−４０１間の転送はできなかった。In the conventional system, CPU MM, CPU←→CH,
It is possible to transfer data between CH44MM and CH44MM, but CH+
Transfer between -401 was not possible.
そのため例えば磁気テープの内容をディスクにコピーす
るような場合、ＭＭ中にバッファ領域ｔと９、まずＭＴ
Ｕ４ＣＨＯ→ＭＷの転送【行い、次ＫＭＭ−＋ＣＨＩ−
＋ＤＰＵの転送上行ない、これを必要回数繰り返すこと
が必要でＴｏＤ、メ峰すＭＭ中にバッファ領域が要るこ
と、及びＣ−ＢＵ８ｔ−２回使用する必要があること等
Ｏ問題を生じていた・
本発明はこの点上解決するものである。そのため本発明
では各チャネル中に所定容量又はそれ以上のバッツアメ
モリ【設けてチャネル間でＮｉ１転送するものである。Therefore, for example, when copying the contents of a magnetic tape to a disk, buffer areas t and 9 in MM are first copied to MT.
U4CHO→MW transfer [perform, next KMM-+CHI-
+ It was necessary to transfer the DPU and repeat this as many times as necessary, which caused problems such as the need for a buffer area in the MM for ToD and mail, and the need to use C-BU8t twice. - The present invention solves this problem. Therefore, in the present invention, a predetermined capacity or more of a buffer memory is provided in each channel, and Ni1 is transferred between the channels.
デバイス間デーー転送に際しては、低速側のデバイスｔ
たは専有が許される側のデバイス、上記の例でｔｚＭＴ
Ｕ儒のチャネルＣＨＩバスマスタとし、ランダムアクセ
ス装置など専有の許されない側のデバイス、上！の例で
ｔ！ＤＰＵ＠のチャネルＣＨ２ｔ−バススレーブとする
。When transferring data between devices, the lower speed device t
or the device on which exclusive use is permitted, in the above example tzMT
As the U Confucian channel CHI bus master, devices on the side that are not allowed to be proprietary, such as random access devices, on! In the example of t! Channel CH2t of DPU@ is assumed to be bus slave.
異体的手順としては、
■ 先ずＣＰＵ・はＭＭ中の所定アドレスに、デバイス
藺転送に必要１に：ｆｆｗンド語を用意すゐ。As an alternative procedure, ■ First, the CPU prepares the 1:ffwn word necessary for device transfer at a predetermined address in the MM.
■ ＣＰＵはＣＨ（ｌ上記アドレスを通知して、ＣＨＯ
Ｋそのアドレスからコマンド１ｌｌｔ−７エツチさ（る
。■ The CPU sends a message to CH(l) by notifying the above address.
The command 1llt-7 is retrieved from that address.
■ ＣＨＯは７エツチしたコマンドを解析する。■ CHO analyzes the 7-etched command.
ここまでの動作は従来の入出力装置起動のシーケンスと
同じである。The operation up to this point is the same as the conventional input/output device startup sequence.
■ 次に本発明で框、ＣＨＯはＣＨＩをバススレーブと
してアドレス指定する０％しＣＨＩ （又はＤＰＵ１若
しくはＣ−ＢＵＳがビジーであればビジーでなくなるま
で待つ。(2) Next, according to the present invention, the CHO addresses CHI as a bus slave (0%) and waits until CHI (or if DPU1 or C-BUS is busy, it is no longer busy).
それとと％ＫＭＴＵから所定容量のデータｖｔＣＨＯ／
（ラフアメそリヘ読出しておく。And a predetermined amount of data vtCHO/from %KMTU
(Read out the rough American sori.
■ バススレーブとの接続が確立したら上記バッファメ
モリ間でデータ転送【行なう、１回の転送が終了したら
一旦Ｃ−ＢＵ８を開放し、各チャネルではバッツアメモ
リとデバイスとの間での転送を行なう、この間Ｃ−ＢＵ
８ｉ他のチャネルやＣＰＵのために使用され得る。ｔた
上記スレーブ側のデバイスも他の処理のために使用され
得る。但し、上記コマンドで指示されたデータ転送はそ
の一部のみしか終了していないので、プログラム上でそ
の点を考慮しないと矛盾を生じることがある拳
■ バッツアメモリとデバイス間での転送が終了すると
バスマスタＣＨＩは再びバススレーブＣＨ２を獲得して
次の所定容量データの転送に入る。以下同様に■〜■を
必要回数繰り返えす。■ Once the connection with the bus slave is established, data is transferred between the buffer memories mentioned above. Once one transfer is completed, C-BU8 is released, and each channel transfers data between the buffer memory and the device. C-BU
8i can be used for other channels and CPUs. The slave side device may also be used for other processing. However, since only a portion of the data transfer instructed by the above command has been completed, if this point is not taken into account in the program, inconsistencies may occur. CHI acquires bus slave CH2 again and starts transferring the next predetermined capacity data. Repeat steps 1 to 2 as many times as necessary.
必Ｗ回数の転送が終了したらＣＨＩはＣＰＵＫ対して終
了割込み會上げで、自らのデノ（イスビジーを落とす、
尚バスマスタＣＨＩはフ−，、）ｄ管受けてから終了割
込み【あけるまではデノ（イスビジー状態でＴｏゐｅｔ
７ｊパススレーブＣＨ２はデータ転送時のみデバイスビ
ジー状態である。When the required number of transfers is completed, CHI sends a termination interrupt to CPUK, dropping its own deno (Isbusy),
In addition, the bus master CHI receives the end interrupt after receiving the d pipe.
7j path slave CH2 is in a device busy state only during data transfer.
第２１１は本発明のためのチャネル装置の一実施例概略
ブロック図であり、ＡＤはアドレスデコーダ、ムＲはア
ドレスレジスタ、ＤＲｒＸデータレジスタ、ＣＭＲはコ
マンドレジスタ、ＣＴＬｔ；コントロール部、ＤＢａデ
ータバッツァメモリ、Ａ−ＢＵ８ｔＸ７ドＶｄ１Ｃパス
、Ｄ−ＢＵ８ｒＸデータノ（ス、ＣＬは制御線である。No. 211 is a schematic block diagram of an embodiment of a channel device for the present invention, where AD is an address decoder, R is an address register, DRrX data register, CMR is a command register, CTLt is a control unit, and DBa data batzer memory. , A-BU8tX7-Vd1C path, D-BU8rX data node (CL) is a control line.
各チャネルはアドレスデコーダＡＤＫＬりて常にム−Ｂ
Ｕ８の値【監視しており、自チヤネル内のレジ鳥りに付
されたアドレスを検出するとＣＴＬＶ介してＤ−ＢＵＳ
上のデータを所定のレジスタへＭＲｇ込む１うにされる
。Each channel is always connected to the address decoder ADKL.
Value of U8 [It is monitored, and when it detects the address attached to the register in its own channel, it sends the D-BUS via CTLV.
The above data is loaded into a predetermined register.
また制御線ＣＬＫは選択信号、同期信号、割込信号等が
含まれるが、これらについては前記先行技術によって全
知でＴｏあので省略する。Further, the control line CLK includes a selection signal, a synchronization signal, an interrupt signal, etc., but these will be omitted since they are all known according to the prior art.
ｔｆｔＩ１０デバイスとの間Ｋに所定容量の〕（ラフア
メモリ−Ｂが設けられる。A rough memory B of a predetermined capacity is provided between the device and the tftI10 device.
以上の如く本発明ではチャネル間直接転送ＫＪＣりＣ−
ＢＵＳの占有が従来のｌ／２の時間で済み、を九ＭＭ中
にバッファ領域が不要になり、ま７ｔＣ−ＢＵ８以外に
図の如くメモリーくスＭ−ＢＵ８Ｔｈ有する場合には両
者の並行動作も可能となり、効率的なシステム運用が可
能となる。As described above, in the present invention, direct transfer between channels KJC and C-
BUS occupancy takes 1/2 of the conventional time, no buffer area is required in 9MM, and if there is memory space M-BU8Th as shown in the figure in addition to 7tC-BU8, parallel operation of both is possible. This makes it possible to operate the system efficiently.
第１図に一般的システム構成図、第２図は本発明の一実
施例ブロック■である。＠中、ＣＨＩはチャネル、ＡＲ
，ＣＭＲ，ＤＲはレジスタ、ＡＤにアドレスデコーダ、
ＣＴＬＨコントロール部、ＤＢｔｚｆ−ｐバッフアメ篭
りである。
屏１１ｉ！Ｉ
（）−−ノ ｃｔＨ
−８ｖ５
耳ｚ６FIG. 1 is a general system configuration diagram, and FIG. 2 is a block diagram of one embodiment of the present invention. @Naka, CHI is channel, AR
, CMR, DR are registers, AD is an address decoder,
CTLH control section, DBtzf-p buffer candy. Folding 11i! I ()--ノ ctH -8v5 ear z6
Claims (1)
通パスＫＩＩ絖された計算機システムにおいて、各チャ
ネル装置にはそのチャネル装置の下位に接続された入出
力装置との間のデータ転送のための所定容量以上のバッ
フ７メそりｔ設け、中央処ｌ装置からのコマンド會うけ
て１つのチャネルｅｌｋ 置ｆａｔ ハスマスタＫｆｉ
ｊ）、該パスマスクが偽のチャネル装置をパススレーブ
として指定し、両チャネル装置間で上記所定容量のデー
タ七直接転送することｔ４１徴とするチャネル装置間デ
ータ転送方式。In a computer system in which at least one central processing unit and a plurality of channel devices are connected to a common path KII, each channel device has a system for data transfer between the input and output devices connected to the lower level of the channel device. Seven buffers with a predetermined capacity or more are provided, and one channel is set up in response to commands from the central processing unit.
j) An inter-channel device data transfer method in which the channel device whose path mask is false is designated as a path slave, and the predetermined amount of data is directly transferred between both channel devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10398181A JPS585824A (en) | 1981-07-03 | 1981-07-03 | Data transferring system between channels |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10398181A JPS585824A (en) | 1981-07-03 | 1981-07-03 | Data transferring system between channels |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS585824A true JPS585824A (en) | 1983-01-13 |
Family
ID=14368487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10398181A Pending JPS585824A (en) | 1981-07-03 | 1981-07-03 | Data transferring system between channels |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS585824A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6118060A (en) * | 1984-07-04 | 1986-01-25 | Nec Corp | Data processing system |
| JPS62147902A (en) * | 1985-12-20 | 1987-07-01 | Fujitsu Ltd | Linear conveyor |
| JPH02162152A (en) * | 1988-12-14 | 1990-06-21 | Itoki Kosakusho Co Ltd | Conveying device |
-
1981
- 1981-07-03 JP JP10398181A patent/JPS585824A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6118060A (en) * | 1984-07-04 | 1986-01-25 | Nec Corp | Data processing system |
| JPS62147902A (en) * | 1985-12-20 | 1987-07-01 | Fujitsu Ltd | Linear conveyor |
| JPH0732521B2 (en) * | 1985-12-20 | 1995-04-10 | 富士通株式会社 | Linear carrier |
| JPH02162152A (en) * | 1988-12-14 | 1990-06-21 | Itoki Kosakusho Co Ltd | Conveying device |
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