JPS5854633A - Microprocessing method - Google Patents
Microprocessing methodInfo
- Publication number
- JPS5854633A JPS5854633A JP56154228A JP15422881A JPS5854633A JP S5854633 A JPS5854633 A JP S5854633A JP 56154228 A JP56154228 A JP 56154228A JP 15422881 A JP15422881 A JP 15422881A JP S5854633 A JPS5854633 A JP S5854633A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- film
- electron beam
- mask
- conductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
- H01J37/3174—Particle-beam lithography, e.g. electron beam lithography
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Analytical Chemistry (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Drying Of Semiconductors (AREA)
- Electron Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、電子ビームを用いた微細加工方法の改良に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in microfabrication methods using electron beams.
近時、半導体ウェーハやマスク基板等に微細な７譬ター
ンを形成するものとして、電子ビーム露光技術を利用し
た微細加工方法が用いられている。電子ビーム露光技術
は光露光技術と異なり、回折に起因する解像力の低下が
ない九め、本質的に微細・ｆターフを容易に形成できる
と云われている。ところが、電子ビームには固体中の散
乱と云う別のｌｓ像力の制限要素があり、これが数〔μ
ｍ〕以下の・譬ターン形成に重大な問題となっている。2. Description of the Related Art Recently, a microfabrication method using electron beam exposure technology has been used to form fine heptad turns on semiconductor wafers, mask substrates, and the like. Unlike light exposure technology, electron beam exposure technology does not reduce resolution due to diffraction, and is said to be essentially capable of easily forming fine f-turfs. However, the electron beam has another factor limiting the ls image power, called scattering in solids, and this
m) The following - parable turn formation has become a serious problem.
第１図は従来の微細加工方法に係わる電子ビーム露光法
を示す模式図である。基板１の上向に形成された被加工
物２上に感電子レジス）Ｊを塗布し、とのレジス）Ｊに
例えば２０（Ｋ＠Ｖ）に加速された電子ビームを照射し
て所望／ｆターンヲ露党する。次いで、レジストＪを現
像し九のち該レジストＪをマスクとして被加工物２を戸
うイエ、チングし、−臂ターン形成を行っている。FIG. 1 is a schematic diagram showing an electron beam exposure method related to a conventional microfabrication method. An electron-sensitive resist (J) is coated on the workpiece 2 formed above the substrate 1, and the resist (J) is irradiated with an electron beam accelerated to, for example, 20 (K@V) to form a desired /f Turn to Russia. Next, the resist J is developed, and then the workpiece 2 is etched using the resist J as a mask to form a -arm turn.
ここで基板１をシリコン、被加工物２を厚さＯ，Ｓ（μ
ｍ〕の酸化シリコン、レゾスト３Ｙｒ厚さ１〔綿〕のｐ
−仏（ポリメチルメタク１ルート）とすると、電子ビー
ムは基板１内の数〔μ畷〕の深さまで到達し、その深さ
から後方散乱する。この後方散乱した電子はレゾス）Ｊ
Ｋ再入射し同レジスト１に、所謂カプリ現象を引き起こ
す、このカプリの及ぶ範囲は電子ビームの径の大きさに
拘らず数〔μｍ） Ｋ達する・そして、レゾストＪを現
像した場合、上記カプリによりレゾスト−ターンの寸法
精度が損われ、と九によｐ数〔＃解〕以下の・ヤターン
を精度良く形成することはできなかった。Here, the substrate 1 is silicon, and the workpiece 2 has a thickness of O, S (μ
m] silicon oxide, Resost 3Yr thickness 1 [cotton] p
-French (polymethylmethac 1 route), the electron beam reaches a depth of several [μ] within the substrate 1, and is backscattered from that depth. This backscattered electron is res)J
When K re-enters the resist 1, it causes the so-called capri phenomenon.The range of this capri reaches several [μm] K, regardless of the diameter of the electron beam.And when resist J is developed, the capri causes the so-called capri phenomenon. The dimensional accuracy of the resist turn was impaired, and it was not possible to form a diameter turn with a number of p or less with high precision.
そこで、上記後方散乱のＩＩ！囲を小さくする手段とし
て、電子ビームのエネルギを小さくすることが試みられ
ている０％に、５ （Ｋ＠Ｖ） 以下Ｏエネルギ和する
と電子ビームの侵入深さが極めて小さくな９、後方散乱
が及ぶ範囲も小さくな炒、ｆｆンクロンの・ナターン形
成に支１ｉＩがなくなる。しかしながら、この場合電子
ビームの侵入深さが小さいためレジスト１の全域を十分
に露光できないと云う問題を生じる。また、電子ビーム
のエネルギを１０（Ｋ＠Ｖ）に設定し九場合にはｓ ２
０（Ｋ＠Ｖ）の場合より多小嵐好な結果が得られるが、
満足できるものではなかった。Therefore, the above-mentioned backscatter II! An attempt has been made to reduce the energy of the electron beam as a means to reduce the energy of the electron beam.If the sum of O energies is less than 5 (K@V), the penetration depth of the electron beam is extremely small9, and backscattering is The area covered is also small, and there is no support 1iI in the formation of ffnkuron. However, in this case, since the penetration depth of the electron beam is small, a problem arises in that the entire area of the resist 1 cannot be sufficiently exposed. Also, if the energy of the electron beam is set to 10 (K@V) and 9, s 2
Although a better result can be obtained than in the case of 0 (K@V),
It wasn't satisfying.
本発明は上記事情を考慮してな畜れたもので、その目的
とするところは、電子ビームの後方敏ＬＫ起因するカプ
リを低減でき、かつレジストを十分に露光でき、微細・
皆ターンを高精度に形成することのできる微細加工方法
を提供することにある。The present invention was developed in consideration of the above circumstances, and its purpose is to reduce the capri caused by the backward sensitivity LK of the electron beam, to sufficiently expose the resist, and to
The object of the present invention is to provide a microfabrication method that can form turns with high precision.
まず、本発明のａＳを説明する。電子ビームの加速電圧
を７（Ｋ＠Ｖ）以下とすると前述しえ如くレジストの十
分な露光は不可能である。このため、電子ビームの加速
電圧は７（Ｋ＠Ｖ）以上にする必要がある。また、ＶＢ
度の高い物質はど電子の侵入深さは浅くなり、それだけ
後方散乱の及ぶ範−が狭くなる。この九め、ある程度高
い密度の物質をある程度以上の膜厚に形成すれば、電子
の侵入を抑制できることになる。そして、本発明者等の
研究によれば、密度りが１０以上の導電膜をＤ 〔μｍ
〕以上の厚さに形成すると、１５（Ｋ＠Ｖ）以下の電子
ビームの侵入は大１１に抑制されることが判った。First, the aS of the present invention will be explained. If the acceleration voltage of the electron beam is set to 7 (K@V) or less, sufficient exposure of the resist is impossible as described above. Therefore, the acceleration voltage of the electron beam needs to be 7 (K@V) or more. Also, VB
In materials with a high density, the penetration depth of electrons becomes shallower, and the range of backscattering becomes narrower. Ninth, if a material with a certain high density is formed to a certain thickness or more, the penetration of electrons can be suppressed. According to research by the present inventors, a conductive film with a density of 10 or more is D [μm
] It was found that when formed to a thickness greater than 1, the penetration of electron beams of 15 (K@V) or less is suppressed to a factor of 11.
本発明はこのような点に着目し、被加工物上に高密度の
導電膜、を形成し、この導電膜上に感電子レジストを形
成したのち、７〜ｌ ５（Ｋ＠Ｖ）に加速された電子ビ
ームを用いてレジストを所望ノｆターンに露光し現像し
、次いでレジストをマスクとして上記導電膜をドライエ
、チンｒし、しかるのち導電膜ｔマスクとして上記被加
工物をドライエ、チンｒするようにした方法である。The present invention has focused on these points, and after forming a high-density conductive film on the workpiece and forming an electrosensitive resist on the conductive film, it is accelerated to 7 to l5 (K@V). The resist is exposed to a desired number of turns using an electron beam, and then developed. Then, using the resist as a mask, the conductive film is subjected to a dry etching process, and then the workpiece is subjected to a dry etching process using a conductive film mask as a mask. This is the method I used to do it.
したがって、本発明によれば、電子ビームの後方散乱を
極めて小さくでき、かつレジストの十分な露光を行うこ
とができる。このため、上記後方散乱に起因する解像力
低下を防止し、数（Ｊ帛〕以下Ｏｄターン會もｊｌ！Ｉ
精変に形成する仁とがてきる。−例として、第２ｍＫ示
す如くレゾスト３０編厚を１［ＪｌｌＩ）、白金（密度
２１４ ｔ／ｄ ）からなる導電膜４のｇ厚ｔ Ｏ，ｌ
（ｓ鯛〕とし、加速電ｆＥ １ Ｇ（Ｋ＠Ｖ）の電子ビ
ームでレゾストＪ’）露光し九とζろ、同図にも示す如
く後方散乱の及ぶ範囲が１８１図に比して著しく小さく
なった。Therefore, according to the present invention, backscattering of the electron beam can be extremely reduced, and the resist can be sufficiently exposed. For this reason, it is possible to prevent the resolution from decreasing due to the backscattering mentioned above, and to reduce the number of Od turns below Jl!I.
The jin that forms in a beautiful way comes. - As an example, as shown in the second mK, the thickness of the resist 30 is 1 [JllI], and the g thickness t O, l of the conductive film 4 made of platinum (density 214 t/d)
(s sea bream) and exposed it with an electron beam of accelerated electric current fE 1 G (K@V) (9 and ζ). It became smaller.
そしてｔｏ場合、ｌ〔μｍ３寸法のＩ豐ターνを高精度
に露光することがで自た。また、被加工物２として絶縁
物ｔ！ｆＩいる場合、導電１１１４が電子ビームによる
チャージアラｆを訪止し、ｚ４ターンの歪を防止できる
等の利点がある。なお、微細加工では通常イオンビーム
エツチング、反応性イオンビームエツチング、反応性ス
／譬、タエ。In the case of to, it was possible to expose with high precision an I-tar ν having a dimension of l [μm3. Further, as the workpiece 2, an insulator t! When there is fI, the conductor 1114 visits the charger f caused by the electron beam, and there are advantages such as being able to prevent distortion of the z4 turn. In microfabrication, ion beam etching, reactive ion beam etching, and reactive etching are usually used.
チンｒ等のドライエツチング用りられるが％導電膜はド
ライエ、チンｒのマスク材として十分使用可能である。Although dry etching such as Chin-R is used, the % conductive film can be sufficiently used as a mask material for Dry etching and Chin-R.
以下、本発明の詳細を図示の実施例によりてｌＩＳ！明
する。The details of the present invention will be explained below with reference to illustrated embodiments. I will clarify.
第３図−）〜（ｄＪは本発明の一実１例に係わる黴ａｍ
／ｅターン形成工程を示す断復模式−であみ。Figure 3-) to (dJ are molds related to one example of the present invention.
/e A cut-and-return model showing the turn forming process.
マス、ＪｌｌＩＳ ｔｌｌＪｋｌＫ示ｆｔ１Ｊ ＜ ｙ
９ ｗ ｙ基１ｉ： Ｉ ｌ 上に熱酸化技術を用い
被加工物としての酸化シリコン膜１２を０．５〔μ講〕
の膜厚に形成し、この酸化シリコン膜１２上にアルｆン
スイ、り蒸着法で白金ＩＩ（導電膜）ＪＪｔＯ，１（μ
調〕の膜厚に形成し、続いて白金膜１３上Ｋ Ｐｌｉｌ
！ＭＡレジスト１４をｌ〔μ講〕の厚さに回転塗布し九
０次いで、電子ビームを用い加速電圧１０（Ｋ＠Ｖ）、
ドーズ量６０（Ｊａ／ｊ）の条件下で、レジスト１４１
１Ｃ１，２ｅ４ 、１０（ｍｓ）の−々ターンを露光し
た。続いてインゾロパノールとメチルインブチルケトン
と。Mass, JllIS tllJklK show ft1J < y
9 w y group 1i: I l A silicon oxide film 12 as a workpiece is formed on the silicon oxide film 12 by 0.5 [μ] using thermal oxidation technology.
Platinum II (conductive film) JJtO,1 (μ
Then, K Pliil was formed on the platinum film 13 to a thickness of
! MA resist 14 was spin-coated to a thickness of 1 [μ], and then an electron beam was used to apply an accelerating voltage of 10 (K@V).
Under the condition of a dose amount of 60 (Ja/j), the resist 141
1C1, 2e4, each turn of 10 (ms) was exposed. Followed by inzolopanol and methylinbutylketone.
混合液でレジスト１４を現像し九ところ、第３図会）に
示す如きレノスト・ナターンが形成されえ。When the resist 14 is developed with the mixed solution, a rennost-natern pattern as shown in FIG. 3 is formed.
なお、第３図会）では前記１（μ溝〕と２〔μ寓）（Ｄ
Ｉ！党部を現像した状態を示している。In addition, in Figure 3), the above 1 (μ groove) and 2 [μ groove] (D
I! It shows the developed state of the party section.
次に、アル♂ンイオンピームエ、チング技櫂を用い、第
３図（＠）に示す如くレジスト１４をマスクとして白金
Ｉ［１ｓｔ−工、チングし九、続いて、７レオンと水素
との混合ガスを反応ガスとする反応性イオン工、チング
技術を用い、第８１１１（ｄ）に示す如く白金１１ＪＪ
をマスクとしてシリコン域化１ｓ１１を工、チングし友
、かくして形成された・＋４−ンは１ 、２ 、４ 、
１０（岸購〕のいずれの寸法であっても精度良いもので
あった。Next, as shown in FIG. 3 (@), using an aluminium ion beam and a chlorine gas, with the resist 14 as a mask, platinum I Platinum 11JJ as shown in Section 8111(d) using reactive ionization and ching techniques as a reactive gas.
The silicon region 1s11 is processed and etched using as a mask.
No. 10 (Kishi-purchased), all dimensions had good accuracy.
なお、上述した実施例てはシリコン基板を用いたが、こ
の代シにガラス基板を用りてもよく、クロム等を被加工
物とする７ｔ）マスクの作製に適用することもできる。Note that although a silicon substrate was used in the above embodiment, a glass substrate may be used instead, and the present invention can also be applied to the production of a 7t) mask in which the workpiece is chromium or the like.
また、導電膜としては白金膜に限るものではなく、密度
の高い物質、好ましくは密度りが１０以上でその膜厚、
がυ 〔綿〕以上のものであればよい、さらに、被加工
物やレノストの材質および膜厚等は、仕ｉａＫ応じて適
宜定めればよい、その他、本発明の要旨を逸脱しない＠
−で、櫨々変形して実施する仁とができる。In addition, the conductive film is not limited to a platinum film, but is a material with high density, preferably a material with a density of 10 or more and a film thickness of
It is sufficient if the material is υ [cotton] or more. Furthermore, the material and film thickness of the workpiece and lenost may be determined as appropriate depending on the specifications, without departing from the gist of the present invention.
-, it is possible to transform the shape and execute it.
ｉａ１図は微細加工方法に係わる従来の電子ビーム露光
法を示す模式図、ｗ４２図は本砧明の原理をｌ！Ｉ！明
するための模式図、第３図（１）〜（ｄ）は本発明の一
実施例に係わる微細・譬ターン形成工程を示す模式−で
ある。
１１・軸シリコン基’ｌ、Ｊ ｘ・−シリコン１１化１
［（被加工物）、ＩＳ・・・白金ＩＩ（導電ＩＩ）、１
４−・レジスト。
出願人代理人 弁理士 鈴 江 武 彦第１図
第２図・Figure ia1 is a schematic diagram showing the conventional electron beam exposure method related to microfabrication method, and figure w42 is a schematic diagram of Akira Motokinuti's principle! I! For clarity, FIGS. 3(1) to 3(d) are schematic diagrams showing the process of forming fine and circular turns according to an embodiment of the present invention. 11・Axis silicon group'l, J x・-Silicon 11 compound 1
[(Workpiece), IS...Platinum II (Conductivity II), 1
4-・Resist. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2
Claims (1)
ｖ）に加速された電子ビームｆ：ＭＪいて上記レジスト
を所望ｐ４ターンに露光した０ち該レジストを現像する
工程と、次いで上記レジストをマスクとして前記導電＠
ｔドライエツチングする工程と、しかるのち上記導電膜
をマスクとして前記被加工物をドライエツチングする工
程とを具備したことを特徴とする微細加工方法。 Ｑ）前記導電膜の密度Ｄｉ−１０以上とし、かつその膜
圧をＤ Ｃμｍ１以上としたことｔｑ＃黴とする特許請
求の範囲第１項記載の微細加工方法。 （３）前記導電膜として、タンタル、白金、金或いはこ
れらの複合物を用いたことを特徴とする特許請求の範囲
第１項又は１８２項記載の微細加工方法。[Claims] a) Elevated position (ic@
v) A step of exposing the resist to a desired p4 turn using an electron beam f:MJ accelerated by MJ, and then developing the resist using the resist as a mask.
1. A microfabrication method comprising the steps of dry etching the workpiece, and then dry etching the workpiece using the conductive film as a mask. Q) The microfabrication method according to claim 1, wherein the conductive film has a density Di-10 or more and a film thickness of D C μm1 or more. (3) The microfabrication method according to claim 1 or 182, wherein tantalum, platinum, gold, or a composite thereof is used as the conductive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56154228A JPS5854633A (en) | 1981-09-29 | 1981-09-29 | Microprocessing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56154228A JPS5854633A (en) | 1981-09-29 | 1981-09-29 | Microprocessing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5854633A true JPS5854633A (en) | 1983-03-31 |
Family
ID=15579647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56154228A Pending JPS5854633A (en) | 1981-09-29 | 1981-09-29 | Microprocessing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5854633A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61288427A (en) * | 1985-06-17 | 1986-12-18 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| JPS63110729A (en) * | 1986-10-29 | 1988-05-16 | Nec Corp | Manufacture of semiconductor device |
| JPH0210356A (en) * | 1988-06-29 | 1990-01-16 | Matsushita Electric Ind Co Ltd | Fine pattern forming material and method therefor |
| US5019485A (en) * | 1988-10-13 | 1991-05-28 | Fujitsu Limited | Process of using an electrically conductive layer-providing composition for formation of resist patterns |
| JPH05326385A (en) * | 1992-05-25 | 1993-12-10 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1981
- 1981-09-29 JP JP56154228A patent/JPS5854633A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61288427A (en) * | 1985-06-17 | 1986-12-18 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
| JPS63110729A (en) * | 1986-10-29 | 1988-05-16 | Nec Corp | Manufacture of semiconductor device |
| JPH0210356A (en) * | 1988-06-29 | 1990-01-16 | Matsushita Electric Ind Co Ltd | Fine pattern forming material and method therefor |
| US5019485A (en) * | 1988-10-13 | 1991-05-28 | Fujitsu Limited | Process of using an electrically conductive layer-providing composition for formation of resist patterns |
| JPH05326385A (en) * | 1992-05-25 | 1993-12-10 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
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