JPS58524U - Malfunction prevention circuit - Google Patents

Malfunction prevention circuit

Info

Publication number
JPS58524U
JPS58524U JP9556881U JP9556881U JPS58524U JP S58524 U JPS58524 U JP S58524U JP 9556881 U JP9556881 U JP 9556881U JP 9556881 U JP9556881 U JP 9556881U JP S58524 U JPS58524 U JP S58524U
Authority
JP
Japan
Prior art keywords
circuit
malfunction prevention
operating
prevention circuit
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9556881U
Other languages
Japanese (ja)
Other versions
JPH0317472Y2 (en
Inventor
孝明 石井
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP9556881U priority Critical patent/JPS58524U/en
Publication of JPS58524U publication Critical patent/JPS58524U/en
Application granted granted Critical
Publication of JPH0317472Y2 publication Critical patent/JPH0317472Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係る誤動作防止回路の一実施−例を示
す図、第2図は本考案に係る誤動作防止回路の他の実施
例を示す図、第3図および第4図はそれぞれ第1図およ
び第2図に示した誤動作防止回路の動作を示すタイミン
グチャートである。 1・・・・・・電子回路、2.3・・・・・・ゲート回
路、4・・・・・・ウィンドコンパレータ、11.12
・・・・・・論理素子、C□、 c2. c3. c、
・・・・・・コンデンサ、R,、R2゜R3,R4,R
5・・・・・・抵抗。
FIG. 1 is a diagram showing one implementation example of the malfunction prevention circuit according to the present invention, FIG. 2 is a diagram showing another embodiment of the malfunction prevention circuit according to the present invention, and FIGS. 3 is a timing chart showing the operation of the malfunction prevention circuit shown in FIGS. 1 and 2. FIG. 1...Electronic circuit, 2.3...Gate circuit, 4...Window comparator, 11.12
...Logic element, C□, c2. c3. c,
・・・・・・Capacitor, R,, R2゜R3, R4, R
5...Resistance.

Claims (4)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)レベルの異なる2つの動作信号によって動作状態
が規制される電子回路の誤動作防止回路において、前記
動作信号をそれぞれ電源の立上りに際して微分特性をも
たせ乞第1の回路および積分特性をもたせる第2の回路
を介して前記電子回路に入力したことを特徴とする誤動
作防止回路。
(1) In a malfunction prevention circuit for an electronic circuit in which the operating state is regulated by two operating signals of different levels, a first circuit in which the operating signals have differential characteristics at the time of power supply rise, and a second circuit in which the operating signals have integral characteristics. A malfunction prevention circuit characterized in that input is input to the electronic circuit through the circuit.
(2)前記第1の回路1よ動作信号を伝送するラインに
直列に挿入された第1の抵抗および該ラインと電源との
間に挿入された第1のコンデンサからなり、前記第2の
回路は動作信号を伝送するラインに直列に挿入された第
2の抵抗および該ラインと接地との間に挿入された第2
のコンデンサからなる実用新案登録請求の範囲第(1)
項記載の誤動作防止回路。
(2) The first circuit 1 is composed of a first resistor inserted in series with a line that transmits an operating signal, and a first capacitor inserted between the line and the power supply, and the second circuit is a second resistor inserted in series with the line transmitting the operating signal, and a second resistor inserted between the line and ground.
Scope of Utility Model Registration Claim No. (1) Consisting of a Capacitor
The malfunction prevention circuit described in section.
(3)前記電子回路はウィンドコンパレータであり、前
記2つの動作信号は該6インドコンパレータの判定基準
電圧である実用新案登録請求の範囲第(1)項記載の誤
動作防止回路。
(3) The malfunction prevention circuit according to claim 1, wherein the electronic circuit is a window comparator, and the two operating signals are determination reference voltages of the six-window comparator.
(4)前記電子回路は論理ローレベルの信号が加えられ
ることによって動作する第1の論理素子と論理ハイレベ
ルの信号が加えられることによって動作する第2の論理
素子とを含んで構成されるものであり、前記2つの動作
電圧はこれら論理素子にそれぞれ加えられる論理ローレ
ベルおよび論理ハイレベルの信号である実用新案登録請
求の範囲第(1)項記載の誤動作防止回路。
(4) The electronic circuit is configured to include a first logic element that operates when a logic low level signal is applied and a second logic element that operates when a logic high level signal is applied. The malfunction prevention circuit according to claim 1, wherein the two operating voltages are logic low level and logic high level signals applied to these logic elements, respectively.
JP9556881U 1981-06-26 1981-06-26 Malfunction prevention circuit Granted JPS58524U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9556881U JPS58524U (en) 1981-06-26 1981-06-26 Malfunction prevention circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9556881U JPS58524U (en) 1981-06-26 1981-06-26 Malfunction prevention circuit

Publications (2)

Publication Number Publication Date
JPS58524U true JPS58524U (en) 1983-01-05
JPH0317472Y2 JPH0317472Y2 (en) 1991-04-12

Family

ID=29890468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9556881U Granted JPS58524U (en) 1981-06-26 1981-06-26 Malfunction prevention circuit

Country Status (1)

Country Link
JP (1) JPS58524U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS422278Y1 (en) * 1964-09-18 1967-02-10

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS422278Y1 (en) * 1964-09-18 1967-02-10

Also Published As

Publication number Publication date
JPH0317472Y2 (en) 1991-04-12

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