JPS58139743U - signal output circuit - Google Patents

signal output circuit

Info

Publication number
JPS58139743U
JPS58139743U JP3660182U JP3660182U JPS58139743U JP S58139743 U JPS58139743 U JP S58139743U JP 3660182 U JP3660182 U JP 3660182U JP 3660182 U JP3660182 U JP 3660182U JP S58139743 U JPS58139743 U JP S58139743U
Authority
JP
Japan
Prior art keywords
output
output circuit
circuit
signal output
high impedance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3660182U
Other languages
Japanese (ja)
Inventor
岩元 伸一
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP3660182U priority Critical patent/JPS58139743U/en
Publication of JPS58139743U publication Critical patent/JPS58139743U/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図である。 1・・・3ステート出力のデジタルIC,2,3・・・
ダイオード、4〜7・・・抵抗、8・・・コンパレータ
、9・・・3ステート出力のバッファ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1... Digital IC with 3-state output, 2, 3...
Diode, 4 to 7...Resistor, 8...Comparator, 9...3-state output buffer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 高レベル状態、低レベル状態および高インピーダンス状
態を出力する出力回路と、この出力回路に結合された出
力バッファ回路と、前記出力回路に結合されその高イン
ピーダンス状iを検出して前記出力バッファ回路の出力
を高インピーダンス状態にする制御信号を発生する制御
回路とを有することを特徴とする信号出力回路。
an output circuit that outputs a high level state, a low level state, and a high impedance state; an output buffer circuit coupled to the output circuit; and an output buffer circuit coupled to the output circuit and detecting the high impedance state i of the output buffer circuit. 1. A signal output circuit comprising: a control circuit that generates a control signal that puts an output in a high impedance state.
JP3660182U 1982-03-16 1982-03-16 signal output circuit Pending JPS58139743U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3660182U JPS58139743U (en) 1982-03-16 1982-03-16 signal output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3660182U JPS58139743U (en) 1982-03-16 1982-03-16 signal output circuit

Publications (1)

Publication Number Publication Date
JPS58139743U true JPS58139743U (en) 1983-09-20

Family

ID=30048025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3660182U Pending JPS58139743U (en) 1982-03-16 1982-03-16 signal output circuit

Country Status (1)

Country Link
JP (1) JPS58139743U (en)

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