JPS5848940A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5848940A
JPS5848940A JP14809281A JP14809281A JPS5848940A JP S5848940 A JPS5848940 A JP S5848940A JP 14809281 A JP14809281 A JP 14809281A JP 14809281 A JP14809281 A JP 14809281A JP S5848940 A JPS5848940 A JP S5848940A
Authority
JP
Japan
Prior art keywords
film
polyacethylene
polyimide film
wiring
polyacetylene
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14809281A
Other languages
Japanese (ja)
Other versions
JPH0117254B2 (en
Inventor
Nobuo Sasaki
伸夫 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14809281A priority Critical patent/JPS5848940A/en
Priority to EP82304904A priority patent/EP0075454B1/en
Priority to DE8282304904T priority patent/DE3277759D1/en
Publication of JPS5848940A publication Critical patent/JPS5848940A/en
Priority to US07/008,139 priority patent/US4761677A/en
Publication of JPH0117254B2 publication Critical patent/JPH0117254B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent deterioration by covering the wiring layer of doped polyacethylene film with the polyimide film. CONSTITUTION:The MOS element is formed on the Si substrate 1, then the polyimide film 14 is formed, the resist mask 16 is provided, and an aperture is formed on the SiO2 film by the dydrazine. Then, the polyacethylene film 11 is laminated thereon, the resist mask 17 is provided, the AsF5 is ion-implanted, and thereby conductive layer 11-2 can be obtained selectively. The polyacethylene is sensible for reaction with O2 in the air and is deteriorated during a long period of time. The polyacethylene wiring layers 11-2,...13-2 are thus laminated and finally the polyimide film 15 is coated and then the element is heated. Thereby, the element is perfectly isolated from external air ensuring that deterioration can be prevented and reliability can be improved.

Description

【発明の詳細な説明】 本発明は半導体装置のうち、新たな配線の保護構造を設
けた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device provided with a new wiring protection structure.

集積回路（ＩＣ）などの半導体装置は益々高密度化・高
集積化されて、表面上に多層配線が形成され、今後更に
積層数が増加する傾向にある。そのため、歩留あるいは
イぎ傾度を良くする多層配線は半読体製造上重用な課題
で、技術提案も多い。そのうち、第１図は従来より広く
用いられている配線構造をもった半導体装置の〜ｒ面図
で、半導体基板１にＭＯ８型半一体素子を設け、表面に
保護層として燐けい−ガラス（ＰＳＧ）膜２を形成し、
それに窓あけしてソースＳおよびドレインＤからの導出
用の第１層配線３を形成し、その上に更にＰ８Ｇ膜４を
介在させて第２層配線５を形成したアルミニウム（Ａ４
）金属からなる２層配線の例である。図のように、第１
層配線８と第１層配線３との接続部分Ｃで社、窓あけし
て配線層を被着させるから、大きく凹凸が生じ、更に積
層数を増やせば、ＩＣ全体として凹凸は一層ひどくなっ
て断線あるいは短絡の危険は増加する。さらに、アルミ
ニウムを第１層配線として形成した後には温変を５００
″Ｃ以上にあげるとＡＩとＳｉｎ、の反応力；おころの
で、ＰＳＧＳ複膜電極窓には、ＰＳＧＳ２Ｏ２極窓と異
な９、窓の縁になだらかなテーパをつけるためのいわゆ
るグラス・フロー技術を使う事力くできない。そのため
、配線層を３層、５層と積み上けることにはためらいが
ある。2. Description of the Related Art Semiconductor devices such as integrated circuits (ICs) are becoming increasingly dense and highly integrated, with multilayer wiring formed on their surfaces, and the number of laminated layers is likely to increase further in the future. For this reason, multilayer wiring that improves yield or thermal gradient is an important issue in the production of semi-readable devices, and there are many technical proposals. Of these, FIG. 1 is a ~r-plane view of a semiconductor device with a wiring structure that has been widely used in the past, in which an MO8 type semi-integral element is provided on a semiconductor substrate 1, and phosphor glass (PSG) is provided as a protective layer on the surface. ) forming a film 2;
Aluminum (A4
) This is an example of a two-layer wiring made of metal. As shown, the first
Since a window is opened at the connection part C between the layer wiring 8 and the first layer wiring 3 to deposit the wiring layer, large irregularities occur, and if the number of laminated layers is further increased, the irregularities will become even worse on the entire IC. The risk of wire breaks or short circuits increases. Furthermore, after forming aluminum as the first layer wiring, the temperature change was reduced to 500%.
``When raised above C, the reaction force of AI and Sin; Therefore, there is hesitation in stacking three or five wiring layers.

したがって、表面上の平坦化および多層のｂ己ｕ層間の
窓あけをしない接続法は重要であり、第２図はそれを改
善した例で、配線層として＆　ＩＪアセチレン（ｐｏｌ
ｙ　ａｃｅｔｙｌｅｎｅ　＋　（（Ｊ））０を用い、導
電型不純物を含まない（ノン・ドープド）ボ１ノアセチ
レン膜ならば絶縁層となり、導電型不純物を含ム（ドー
プド）ポリアセチレン膜ならば導電層となることを利用
している。形成法はメンドープドポリアセチレン膜を成
長し、通常のフォト工程でパターンをつけられたレジス
トをマスクとしたイオン注入法により、選択的に不純物
を導入して配線とするもので、第２図は第１図と同じ＜
ＭＯ８型半導体素子の２層配線構造を示す。第１層のポ
リアセチレン膜はゲート′心極Ｇ上では絶縁層１１−１
とし、ソースＳおよびドレインＤから配線１１−２を導
出し、第２層のポリアセチレン膜は全体を絶縁層１２−
１とし、−ｍの接続部分校−１２だけ４電性とする。第
８１ｍのポリアセチレン膜も同様にして絶縁層Ｌ３−１
に選択的に４１１性配６１３−２を形成している。この
ようにすれば絶縁体に窓あけする必要がなく、素子表面
上の平炬度はそのまま劣化なしに、多層化することがＯ
Ｔ比であり、８層、５層としても一１線などが増加する
恐れはない。Therefore, planarization on the surface and a connection method that does not open windows between multi-layered BU and U layers are important. Figure 2 shows an example of this improvement, using &IJ acetylene (pol) as the wiring layer.
If y acetylene + ((J))0 is used, a non-doped polyacetylene film containing no conductivity type impurities will serve as an insulating layer, and a doped polyacetylene film containing conductivity type impurities will serve as a conductive layer. It takes advantage of becoming. The formation method is to grow a men-doped polyacetylene film and selectively introduce impurities into the wiring using an ion implantation method using a resist patterned in a normal photo process as a mask. Same as Figure 1<
A two-layer wiring structure of an MO8 type semiconductor device is shown. The first layer of polyacetylene film is an insulating layer 11-1 on the gate' center pole G.
The wiring 11-2 is led out from the source S and the drain D, and the second layer polyacetylene film is entirely covered with an insulating layer 12-2.
1, and only the connection part of -m -12 is made tetraelectric. Similarly, the 81st polyacetylene film is also applied to the insulating layer L3-1.
A 411 pattern 613-2 is selectively formed in the 411 layer. In this way, there is no need to open a window in the insulator, and the flatness on the element surface remains unchanged, making it possible to create multiple layers.
It is a T ratio, and there is no fear that the number of lines will increase even if there are 8 layers or 5 layers.

しかしながら、ポリアセチレン膜は金属とは異なり、有
機物であって、空気中の酸素との反応が敏感で、長期間
触れさそておけば僅かながら劣化してゆく傾向にある。However, unlike metals, polyacetylene films are organic substances and are sensitive to reactions with oxygen in the air, and tend to deteriorate slightly if left uncontacted for a long period of time.

従って、本発明はこのような欠点を防止することを目的
と１その特徴はポリイミド膜によって被覆されたポリア
セチレン膜からなる配線層が設けられた半導体装置を提
案するもので、以下詳細に説明す・る。Therefore, the present invention aims to prevent such drawbacks and proposes a semiconductor device having a wiring layer made of a polyacetylene film covered with a polyimide film. Ru.

ポリアセチレンは基板にチーグラー・ナツタ触媒を塗布
した後、低温でアセチレンガス雰囲気に曝すと、フィル
ム状に成長するが、半導体としての性質をも持っており
、不純物を含まなければ、電気伝導度１０−’／ｎｃＭ
の絶縁体であるが、例えば万邦化砒素（Ａ、Ｆ、）を含
むと、Ｐ型となって電気伝導度は１０３１０ｃ１１以上
にもなる。したがって、ノンドープドピリアセチレン膜
を成長し、リソグラフィ技術を用いて選択的に不純智を
ドープする。When polyacetylene is coated with a Ziegler-Natsuta catalyst on a substrate and then exposed to an acetylene gas atmosphere at low temperatures, it grows into a film, but it also has properties as a semiconductor, and if it does not contain impurities, it has an electrical conductivity of 10- '/ncM
However, if it contains, for example, arsenic (A, F, ), it becomes P-type and has an electrical conductivity of 10310c11 or higher. Therefore, a non-doped piriacetylene film is grown and selectively doped with impurities using lithography techniques.

ドープの方法はイオン注入法、エレクｌｐケミカルドー
ピング法、あるいは拡散法で行う。こうして平坦な配線
層とすることができる。しかしながら、長期間空気中に
放置すればこれらの電気伝導度は極めて徐々に劣化する
。The doping method is an ion implantation method, an electric lp chemical doping method, or a diffusion method. In this way, a flat wiring layer can be obtained. However, if left in the air for a long period of time, their electrical conductivity deteriorates very gradually.

そのため、この様なポリアセチレン膜で形成した多層配
線をポリイミド膜で被覆させることによって、数年ない
しは半永久的に劣化を抑止させようとするものである０
ポリイミド膜は耐熱性樹脂膜で、リングラフィ技術によ
ってパターンニングができるため、非常に好都合であり
、第３面は一実施例の断面図を示す。血中、１４　、１
５はホ゛リイミド膜で、表面は空気とポリアセチレン膜
１３−１゜１３−２が触れないようにポリイミド膜圧で
被覆してあり、又半導体素子上は通常酸化シリコン（Ｓ
＋Ｏ□）膜やＰＳＧ膜で仮置されているから、これに含
まれる酸素と接触するのを防ぐため、底部にもポリイミ
ド膜１４を形成しである。このようにして被覆しておけ
ばポリアセチレン膜の変質は防止され、且つ半導体基板
１と接する露出部分即ちソースＳドレインＤと接する部
分は酸素が存在しないので劣化の心配はない。Therefore, attempts are being made to suppress deterioration for several years or semi-permanently by covering multilayer wiring formed with such a polyacetylene film with a polyimide film.
The polyimide film is a heat-resistant resin film and is very convenient because it can be patterned by phosphorography technology.The third side shows a cross-sectional view of one embodiment. blood, 14, 1
5 is a polyimide film, the surface of which is covered with polyimide film thickness so that air and the polyacetylene films 13-1 and 13-2 do not come into contact with each other, and silicon oxide (S) is usually used on semiconductor elements.
Since it is temporarily placed with a +O□) film or a PSG film, a polyimide film 14 is also formed on the bottom to prevent it from coming into contact with the oxygen contained therein. By covering in this manner, deterioration of the polyacetylene film is prevented, and there is no risk of deterioration since oxygen does not exist in the exposed portions in contact with the semiconductor substrate 1, that is, in the portions in contact with the sources S and drains D.

次に製造法を要部のみ説明すると、第４図、第５図にそ
の工程途中図を示している。第４図は半導体基板１にＭ
Ｏ８型半導体素子を形成し、その上にスピンコーターで
ポリイミドを塗布し、２００〜８００℃、１時間熱処理
して厚さ４０００〜５０００人のポリイミド膜１４を形
成し、その上面にレジスト膜用をパターンニングした工
程図である。そして、露出したポリイミド膜１４をヒド
ラジンで数分間エツチングして、ソースＳとドレインＤ
の部分に電極を引き出すための窓をあける。このように
して、ポリイミドはパターンニングすることができ、半
導体素子上のｓｉｏ、膜は隔離される。次いで、第５面
はその上面にポリアセチレン膜１１を成長し、レジスト
膜ηをパターンニングして、Ａｓ　Ｆ５をイオン注入・
した工程図を示す。Ａ、Ｆ、がイオン注入されたポリア
セチレン膜は導電体１１−２となり、レジスト膜νで被
覆された部分は絶縁体ｎ　−１のま＼残る。かようにし
てポリアセチレン膜を順次に積層し、最後に再びポリイ
ミド膜迅を塗布し、熱処理すると完全にポリアセチレン
膜はマスクされる。Next, only the main parts of the manufacturing method will be explained. FIGS. 4 and 5 show diagrams showing the process in progress. Figure 4 shows M on the semiconductor substrate 1.
An O8 type semiconductor element is formed, polyimide is applied thereon using a spin coater, and heat treated at 200 to 800°C for 1 hour to form a polyimide film 14 with a thickness of 4,000 to 5,000 thick. It is a process diagram of patterning. Then, the exposed polyimide film 14 is etched with hydrazine for several minutes to form the source S and drain D.
Open a window to pull out the electrode. In this way, the polyimide can be patterned and the SIO film on the semiconductor device isolated. Next, on the fifth surface, a polyacetylene film 11 is grown, a resist film η is patterned, and AsF5 is ion-implanted.
The process diagram is shown below. The polyacetylene film into which A and F are ion-implanted becomes a conductor 11-2, and the portion covered with the resist film ν remains as an insulator n-1. In this way, polyacetylene films are sequentially laminated, and finally, a polyimide film is applied again and heat treated to completely mask the polyacetylene film.

以上は一実施例の説明であるが、このようにポリアセチ
レン膜からなる配線層や絶縁層をポリイミド膜で被覆す
ると、その劣化がなくなるため、高集積化した半導体装
置の信頼性向上に大いに役立つものである。The above is an explanation of one embodiment, but coating the wiring layer and insulating layer made of polyacetylene film with polyimide film eliminates their deterioration, which is greatly useful for improving the reliability of highly integrated semiconductor devices. It is.

【図面の簡単な説明】[Brief explanation of drawings]

第１図および第２図は従来の半導体装置の断面図、第３
図は本発明にか−る半導体装置の断面図、第４図および
第５図はその製造工程途中図である。 図中、１は半導体基板、１１−１　、１２−１　、１３
−１はポリアセチレン膜からなる絶縁体、１１−２．１
２−２．１３−２はポリアセチレン膜からなる導電体、
１４　、１５はポリイミド膜を示す。 第１図 第２図 第４Ｌ℃ 第５図 ７Figures 1 and 2 are cross-sectional views of conventional semiconductor devices;
The figure is a sectional view of a semiconductor device according to the present invention, and FIGS. 4 and 5 are views showing the process of manufacturing the same. In the figure, 1 is a semiconductor substrate, 11-1, 12-1, 13
-1 is an insulator made of polyacetylene film, 11-2.1
2-2.13-2 is a conductor made of polyacetylene film,
14 and 15 indicate polyimide films. Figure 1 Figure 2 Figure 4 L°C Figure 5 7

Claims (1)

【特許請求の範囲】 ポリイミド膜によって被覆されたポリアセチレン膜が設
けられたことを特徴とする半導体装置。 明[Scope of Claims] A semiconductor device characterized by being provided with a polyacetylene film covered with a polyimide film. Akira
JP14809281A 1981-09-18 1981-09-18 Semiconductor device Granted JPS5848940A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP14809281A JPS5848940A (en) 1981-09-18 1981-09-18 Semiconductor device
EP82304904A EP0075454B1 (en) 1981-09-18 1982-09-17 Semiconductor device having new conductive interconnection structure and method for manufacturing the same
DE8282304904T DE3277759D1 (en) 1981-09-18 1982-09-17 Semiconductor device having new conductive interconnection structure and method for manufacturing the same
US07/008,139 US4761677A (en) 1981-09-18 1987-01-22 Semiconductor device having new conductive interconnection structure and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14809281A JPS5848940A (en) 1981-09-18 1981-09-18 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5848940A true JPS5848940A (en) 1983-03-23
JPH0117254B2 JPH0117254B2 (en) 1989-03-29

Family

ID=15445054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14809281A Granted JPS5848940A (en) 1981-09-18 1981-09-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5848940A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0630820U (en) * 1992-09-16 1994-04-22 日信工業株式会社 Rotating lever mounting structure
WO1998021755A3 (en) * 1996-11-12 1998-10-08 Ibm Patterns of electrically conducting polymers and their application as electrodes or electrical contacts
US6331356B1 (en) 1989-05-26 2001-12-18 International Business Machines Corporation Patterns of electrically conducting polymers and their application as electrodes or electrical contacts
US6746770B1 (en) * 1989-05-26 2004-06-08 Internatonal Business Machines Corporation Electrically conductive and abrasion/scratch resistant polymeric materials, method of fabrication thereof and uses thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5351985A (en) * 1976-10-22 1978-05-11 Hitachi Ltd Semiconductor wiring constitution

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5351985A (en) * 1976-10-22 1978-05-11 Hitachi Ltd Semiconductor wiring constitution

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331356B1 (en) 1989-05-26 2001-12-18 International Business Machines Corporation Patterns of electrically conducting polymers and their application as electrodes or electrical contacts
US6746770B1 (en) * 1989-05-26 2004-06-08 Internatonal Business Machines Corporation Electrically conductive and abrasion/scratch resistant polymeric materials, method of fabrication thereof and uses thereof
US7095474B2 (en) 1989-05-26 2006-08-22 International Business Machines Corporation Patterns of electrically conducting polymers and their application as electrodes or electrical contacts
JPH0630820U (en) * 1992-09-16 1994-04-22 日信工業株式会社 Rotating lever mounting structure
WO1998021755A3 (en) * 1996-11-12 1998-10-08 Ibm Patterns of electrically conducting polymers and their application as electrodes or electrical contacts

Also Published As

Publication number Publication date
JPH0117254B2 (en) 1989-03-29

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