JPS5941853A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS5941853A JPS5941853A JP15150682A JP15150682A JPS5941853A JP S5941853 A JPS5941853 A JP S5941853A JP 15150682 A JP15150682 A JP 15150682A JP 15150682 A JP15150682 A JP 15150682A JP S5941853 A JPS5941853 A JP S5941853A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- aluminum
- film
- connection pad
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ）発明の技術分野
本発明は半導体装置及びその製造方法に係り、特に純ア
ルミニウム若しくはその合金によりなるアルミニウム配
線が形成される半導体装置及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device in which aluminum wiring made of pure aluminum or an alloy thereof is formed and a method for manufacturing the same.
（ｂ） 従来技術と問題点
ＭＩＳＩＣやバイポーラＩＣ等の半導体装置ｌこ於ては
、従兼からアルミニウム（Ａｔ）配線が多く用いられて
いる。又層間成るいは表面保饅（カバー）等の絶縁膜に
はりん珪酸ガラス（ＰＳＧ ）膜が多用されて２つ、従
来構造ｌこ於ては前記Ａｔ配線が前記ｐｓａｍ＋ｃ直に
埋設されてなっていた。(b) Prior Art and Problems In semiconductor devices such as MISICs and bipolar ICs, aluminum (At) wiring is often used. In addition, a phosphosilicate glass (PSG) film is often used as an insulating film between layers or as a surface protection (cover).In the conventional structure, the At wiring is buried directly in the psam+c. was.
しかし、上記ＰＳＧＰＡは水と反応してＡｔを腐食する
りん酸（ＨＢ ＰＯ４）を生成する性質があるので、上
記従来構造の半導体装置に於て、パッケージの密封が不
完全である場合等には、半導体装置内に浸入した湿気が
ＰＳＧ膜と反応し、生成したりん酸がＡｔ配線を腐食し
て該配線の劣化や断線を招き、半導体装置の信頼性が低
下するという問題があった。However, the PSGPA has the property of reacting with water to generate phosphoric acid (HBPO4) that corrodes At. There was a problem in that moisture that entered the semiconductor device reacted with the PSG film, and the generated phosphoric acid corroded the At wiring, leading to deterioration and disconnection of the wiring, resulting in a decrease in the reliability of the semiconductor device.
（ｃ） 発明の目的
本発明は上記間頌点に鑑み、アルミニウム配線の表面に
りん酸に対する保護膜を設けた半導体装置及びその製造
方法を提供し、アルミニウム配線を具備し、且つ該配線
かりん珪酸ガラス絶縁膜に直ｌこ埋設される半導体装置
の信頼性を向上せしめることを目的とする。(c) Purpose of the Invention In view of the above points, the present invention provides a semiconductor device in which a protective film against phosphoric acid is provided on the surface of an aluminum wiring, and a method for manufacturing the same, which comprises an aluminum wiring and in which the wiring is made of phosphoric acid. The purpose of this invention is to improve the reliability of a semiconductor device directly embedded in a glass insulating film.
（ｄ） 発明の構成
即ち本発明は配線接続パッド部以外の表面船こプラズマ
酸化による酸化アルミニウム膜が選択的ｔこ形成された
アルミニウム配線が、該配線の配線接続パッド部上に配
線接続窓を有するりん珪酸カラス絶縁膜ｔこ埋込ま扛て
なることを特徴とする半導体装置と、アルミニウム配線
の配線接続パッド上をプラズマ遮蔽膜で選択的に覆って
プラズマ酸化処理を行い、該アルミニウム配憩の表出面
上に選択的に酸化アルミニウム膜を形放し、前記プラズ
マ遮蔽膜を除去した後、該アルミニウム配線形成面上に
、該配線の配線接続パッド部上（こ配線接続窓を有する
りん珪酸ガラス絶縁膜を形成する工程を有することを特
徴とする上記半導体装置の製造方法、及びアルミニウム
配線の配線接続パッド土を耐熱性を有するプラズマ遮蔽
膜で選択的ｔこしってプラズマ酸化処理を行い、該アル
ミニウム配線の表出面上（こ選択的に酸化アルミニウム
膜を形成した後、該アルミニウム配線形成面上にりん珪
酸ガラス絶ｆ禄膜を形成し、該りん珪酸ガラス絶縁膜に
於ける前記アルミニウム配線の配腺援続パッド上に配線
接続窓を形成し、次いで該配線接続窓内に表出せしめら
ｊた前記プラズマ遮蔽膜を除去して該配線接続窓内Ｉこ
前記アルミニウム配線の配球接続パッド部を表出せしめ
る工程を有することを特命とする上記半導体装置の製造
方法ζこ関するものである。(d) Structure of the Invention That is, the present invention is characterized in that an aluminum wiring on which an aluminum oxide film is selectively formed by plasma oxidation on the surface other than the wiring connection pad part has a wiring connection window on the wiring connection pad part of the wiring. A semiconductor device characterized by having a phosphosilicate glass insulating film embedded therein and a plasma shielding film selectively covering the wiring connection pad of the aluminum wiring and performing plasma oxidation treatment to remove the aluminum wiring. After selectively releasing an aluminum oxide film on the exposed surface and removing the plasma shielding film, a phosphosilicate glass insulator having a wiring connection window is placed on the aluminum wiring formation surface on the wiring connection pad portion of the wiring (this is a phosphosilicate glass insulating film having a wiring connection window). The method for manufacturing a semiconductor device as described above is characterized by comprising the step of forming a film, and selectively scraping the wiring connection pad soil of the aluminum wiring with a heat-resistant plasma shielding film and subjecting it to plasma oxidation treatment. After selectively forming an aluminum oxide film on the exposed surface of the wiring, a phosphosilicate glass insulation film is formed on the aluminum wiring formation surface, and the aluminum wiring is arranged on the phosphosilicate glass insulation film. A wiring connection window is formed on the wiring connection pad, and then the plasma shielding film exposed in the wiring connection window is removed, and the wiring connection pad portion of the aluminum wiring is formed inside the wiring connection window. The present invention relates to a method for manufacturing the semiconductor device described above, which is specially designed to include a step of exposing the semiconductor device.
（ａ） 発明の実施例
以下本発明を実施例について、図を用いて詳細に説明す
る。(a) Embodiments of the Invention The present invention will be described in detail below with reference to the drawings.
第１図は本発明の構造を有する半導体装置ｌこ於ける一
実施例の要部断面図、第２図（イ）乃至（ホ）は本発明
の方法の一実施例に於ける工程断面図で、第３図（イ）
、（ロ）は本発明の方法の他の一実施例に於Ｉる工程断
面図である。FIG. 1 is a cross-sectional view of essential parts of an embodiment of a semiconductor device having the structure of the present invention, and FIGS. 2(A) to (E) are process cross-sectional views of an embodiment of the method of the present invention. So, Figure 3 (a)
, (b) are process cross-sectional views in another embodiment of the method of the present invention.
本発明の構造を有するバイポーラＩＣは、例えば第１図
に示すように、ｐ十型アイソレージ言ン領埴１により分
離された第１のｎ型エピタキシャル層２に、＃ｎ型エピ
タキシャル層２からなるｎ型コレクタ領域、該コレクタ
領域２内に形成されたｐ型ベース領域３、該ｐ型ベース
領域３内ｌこ形成されたｎ生型エミッタ領域４、及びコ
レクタ領域２面に形成されたｎ中型コレクタ・コンタク
ト領域５からなるｎｐｎ ）ランジスタが、第２のｎ
型エピタキシャル層６にｐ型抵抗層７等が形成された通
常の基板構造を有している（８はｐ警手導体基板、９は
ｎ＋型埋没層）。A bipolar IC having the structure of the present invention, for example, as shown in FIG. An n-type collector region, a p-type base region 3 formed within the collector region 2, an n-type emitter region 4 formed within the p-type base region 3, and an n-medium type emitter region formed on the second surface of the collector region. An npn) transistor consisting of a collector contact region 5 is connected to a second npn
It has a normal substrate structure in which a p-type resistive layer 7 and the like are formed on a type epitaxial layer 6 (8 is a p-type conductor substrate, 9 is an n+ type buried layer).
また該基板面には通常通り二酸化シリコン（ＳｉＯｚ）
等からなる下履絶縁１１ｉ１０が形成さ扛ており、該下
層絶縁膜１０１こ前記ｐ型ベース領域３、ｎ生型エミッ
タ領域４、ｎ十壓コレクタ・コンタクト領域５、ｐ型抵
抗層７の両端部をそれぞれ表出する電極コンタクト窓１
１が設けられている。Also, silicon dioxide (SiOz) is deposited on the substrate surface as usual.
A lower insulating film 101 consisting of the p-type base region 3, the n-type emitter region 4, the n-type collector contact region 5, and both ends of the p-type resistance layer 7 is formed. Electrode contact window 1 that exposes each part
1 is provided.
そして該下層絶縁膜１０上に、本発明の特徴である表出
面にプラズマ酸化処理で形成された酸化アルミニウム膜
１２を有する純アルミニウム（Ａｚ）若しくはｐｔ金合
金らなるＡｔ配紛即ち例えば前記ベース領域３と抵抗層
７の一端部を接続するＡｔペース配線１３、抵抗層７の
他端から下層絶縁膜１０上に延出烙れ先端部に酸化アル
ミニウム膜１２が選択的に形成さ庇ていない配線接続パ
ッド上１４′を有するＡｔ出力配線１４、及びＡｔエミ
ッタ配線１５、Ａｔコレクタ配線１６等が配設されてお
り、これら配線の形成面上（こ、出力配、線１４の配線
接続パッド１４′上にワイヤ・ボンディング用の配線接
続窓１７を有するりん珪酸ガラス（ＰＳＧ）カバー絶縁
膜１８が形成されてなっている。Then, on the lower insulating film 10, an At dispersion made of pure aluminum (Az) or a PT gold alloy having an aluminum oxide film 12 formed by plasma oxidation treatment on the exposed surface, which is a feature of the present invention, i.e., the base region 3 and one end of the resistor layer 7, an unprotected wire extending from the other end of the resistor layer 7 onto the lower insulating film 10 and having an aluminum oxide film 12 selectively formed on the burnt tip. An At output wiring 14 having a connection pad 14', an At emitter wiring 15, an At collector wiring 16, etc. are arranged, and on the formation surface of these wirings (this, output wiring, wiring connection pad 14' of the line 14) A phosphosilicate glass (PSG) cover insulating film 18 having a wiring connection window 17 for wire bonding is formed thereon.
なお上記実施例に於ては本発明を一層Ａｔ配線構造につ
いて説明したが、本発明は更ｉこＰＳＧ層間絶縁膜を用
いる多層Ａ４配線構造にも適用される。そしてこの場合
各層のＡｔ配線の配線接続パッド部を除く表面にプラズ
マ酸化による酸化アルミニウム膜が形成される。In the above embodiments, the present invention has been described with respect to a single layer At wiring structure, but the present invention is also applicable to a multilayer A4 wiring structure using a PSG interlayer insulating film. In this case, an aluminum oxide film is formed by plasma oxidation on the surface of the At wiring in each layer except for the wiring connection pad portion.
上記本発明の構造を有する半導体装置を製造するに際し
ては、先ず通常のバイポーラＩＣの製造方法Ｉこ従って
半導体基板面に例えばｎｐｎ ）ランジスタ、ｐ型紙抗
層等の形成を行った後、通常通り表面の絶縁膜に電極コ
ンタクト窓を明ける。In manufacturing the semiconductor device having the structure of the present invention, first, according to the usual bipolar IC manufacturing method I, for example, NPN) transistors, p-type paper anti-layers, etc. are formed on the semiconductor substrate surface, and then the surface of the semiconductor substrate is formed as usual. An electrode contact window is opened in the insulating film.
第２図（イ）は上記工程完了後の基板面の要部断面を示
したもので、図中ｌはｐ十型アイソレージ冒ン領域、２
はｎ型コレクタ領域、３はｐ型ベース領域、６はｎ型エ
ビクキシャル層、７はｐ型紙抗層、８はｐ型半導体基板
、９はｎ＋型埋没層、１０は５ｉｎｓからなる下層絶縁
膜、１１は電極コン次いで蒸着、フォトエンチング法等
を用いる通常のＡｔ配線（純Ａｔ若しくはＡｔ合金から
なる）形成方法に従って、第２図（ロ）に示すように、
ｐ型ベース領域３とｐ型抵抗層７の一端ＩＢを仄紗する
Ａｔペース配絹】３、ｐ型抵抗層７の他端部から下層絶
縁ｖ！１０上に延出された先端に１ｊｒｌ線接続パッド
部（ボンディング・パッド）１４′を有するＡｔ出力配
線１４及びしく）示しない領域のＡｔエミッタ配線、Ａ
ｔコレクタ配線等を形成する。FIG. 2(a) shows a cross section of the main part of the substrate surface after the above process is completed, in which l indicates the p-type isolation region, 2
is an n-type collector region, 3 is a p-type base region, 6 is an n-type evixial layer, 7 is a p-type paper antilayer, 8 is a p-type semiconductor substrate, 9 is an n + type buried layer, 10 is a lower insulating film consisting of 5ins, 11 is an electrode conductor, and as shown in FIG. 2 (b), following the usual method of forming At wiring (made of pure At or At alloy) using vapor deposition, photo-etching method, etc.
3. Lower layer insulation from the other end of the p-type resistance layer 7 v! At output wiring 14 having a 1jrl line connection pad portion (bonding pad) 14' at the tip extending above 10 and At emitter wiring in a region not shown (A)
t-Collector wiring etc. are formed.
次いで第２図（−９に示すように、Ａｔ出力配線１４の
配線接続パッド部（ボンティング・パット）１４’上を
プラズマ遮蔽膜例えば］、０００［Ａ：Ｉ’ｌ１度の厚
さの多結晶Ｓｉ膜１９で選択的に覆って、例えば０．１
〜０．５ ［Ｔｏｒｒ、］ ％度の酸素（０２）雰囲気
中ζこ於て２．４５ ＣＧＨｚ ：］若しくは］ ３．
５６ ＣＭ Ｈｚ ］の高周波を用いてプラズマ酸化を
行い、前記多結晶Ｓｉ腫１９に覆わ扛ていないＡｌｌ！
Ｉ１２線即ち出力配線１４、ペース配線１３及び図示し
ないエミッタ配線、コレクタ配線等の表出ｍ１１こむ１
０〜数１００〔λ〕程度の厚さのプラズマ酸化膜（酸化
アルミニウム膜）１２を形成する。Next, as shown in FIG. 2 (-9), a plasma shielding film having a thickness of 1 degree, 000 [A: selectively covered with a crystalline Si film 19, for example, 0.1
~0.5 [Torr,] 2.45 CGHz in an oxygen (02) atmosphere:] or] 3.
Plasma oxidation was performed using a high frequency of 56 CM Hz] to remove All!
I12 line, that is, output wiring 14, pace wiring 13, emitter wiring (not shown), collector wiring, etc. exposed m11 komu 1
A plasma oxide film (aluminum oxide film) 12 having a thickness of about 0 to several 100 [λ] is formed.
次いで本発明の第１の方法に於ては、通常のプラズマエ
ツチング法等ｌこより、前記多結晶Ｓｉ膜１９を選択的
に除去し、第２図に）に示すようにＡｔ出力配線１４の
配線接続パッド（ボンディング・パッド）１４′の上面
を表出させる。Next, in the first method of the present invention, the polycrystalline Si film 19 is selectively removed by a conventional plasma etching method, etc., and the wiring of the At output wiring 14 is removed as shown in FIG. The upper surface of the connection pad (bonding pad) 14' is exposed.
そして第２図（ホ）に示すように、該基板上ｌこ通常の
化学気相成長（ＣＶＤ）法を用いて例えば１〔μｍ）６
度の厚さのＰＳＧカバー絶縁膜１８を形成し、次いで通
常のフォト・エツチング法ｌこより該ＰＳＧカバー絶縁
Ｍ１８にＡｔ出力配線１４の配線接続パッド（ボンデイ
ンク・パラ）”）１４’面を表出するワイヤ・ボンディ
ング用の配線接続窓１７を形成し、本発明のバイポーラ
ＩＣ素子が提供される。Then, as shown in FIG. 2(E), a film of 1 [μm] 6 cm is deposited on the substrate using a conventional chemical vapor deposition (CVD) method.
A PSG cover insulating film 18 with a thickness of approximately 100 mL is formed, and then the wiring connection pad (bond ink/parameter) 14' surface of the At output wiring 14 is exposed on the PSG cover insulating film 18 by a normal photo-etching method. The bipolar IC device of the present invention is provided by forming a wiring connection window 17 for wire bonding.
又本発明の第２の方法に於ては、第２図（ハ）及び第３
図（イ）に示すようにＡｔ出力配線１４の配線接続パッ
ド部（ボンディング・パッド）１４′上をプラズマ遮蔽
腰仙えば１０００（Ａ）程度の厚さの多結晶Ｓｉ膜１９
で選択的に覆って、該多結晶Ｓｉ膜１９に覆われていな
いＡｔ配線即ち出力配線１４、ベース配線１３及び図示
しないエミッタ配線、コレクタ配線等の表出面に数１０
〜数１００〔Ａ）程度の浮式のプラズマ酸化膜１２を形
成した後、第３図（イ）に示すように、該基板上に通常
のＣＶＤ法を用いて例えばＪ早さｌ〔μｍ〕程度のＰＳ
Ｇカバー絶蘇膜１８を形成する・
次いで該ＰＳＧカバー絶縁絶縁膜１屹上力配線１４の配
線接続パッド部１４′の上部を表出するエツチング窓２
０を有するレジス）１１％２１を形成し、該レジス）８
２１をマスクｌこして四弗化炭素（ＣＦ’４）等による
通常のプラズマ・エツチング処理を行い、レジス）１４
９２１のエツチング窓２０内に表出するＰＳＧカバー絶
縁股１８及び多結晶５ｉｌｊ１９を選択的にエツチング
除去し、次いでレジス）ｆｌｉ２１を除去する。In addition, in the second method of the present invention, FIGS.
As shown in Figure (A), a polycrystalline Si film 19 with a thickness of approximately 1000 (A) is placed on the wiring connection pad (bonding pad) 14' of the At output wiring 14 for plasma shielding.
and selectively cover the exposed surfaces of the At wirings not covered with the polycrystalline Si film 19, that is, the output wiring 14, the base wiring 13, and the emitter wiring and collector wiring (not shown).
After forming a floating plasma oxide film 12 with a thickness of about 100 [A], as shown in FIG. degree of PS
Forming the G cover resuscitation film 18. Next, etching window 2 exposing the upper part of the wiring connection pad portion 14' of the force wiring 14 above the PSG cover insulation film 1.
0, forming a register) 11% 21, and forming a register) 8
21 is masked and subjected to ordinary plasma etching treatment using carbon tetrafluoride (CF'4), etc., and resist) 14
The PSG cover insulating crotch 18 and polycrystal 5ilj 19 exposed in the etching window 20 of 921 are selectively etched away, and then the resist 21 is removed.
以上により第３図（ロ）に示すように、ＰＳＧカバー絶
縁膜１１０こ形成テ扛たワイヤ・ボンディング用の配ｍ
接続窓１７内にプラズマ酸化膜（酸化アルミニウム膜）
の形成されていない配線接続パッド１４′面が表出しＰ
ＳＧカバー絶縁股１８に埋込まれた領域の表面ｌこはプ
ラズマ酸化膜（酸化アルミニウム膜）１２を有するＡｔ
配線即ちＡｔ出力配線１４、Ａｔベース配＠１３及び図
示されないＡｔエミッタ配線、Ａｔコンクタ配線等を有
する本発明のバイポーラＩＣが掃供される。As shown in FIG. 3(B), the PSG cover insulating film 110 is formed and the wire bonding layout is formed.
Plasma oxide film (aluminum oxide film) inside the connection window 17
The wiring connection pad 14' surface on which is not formed is exposed P.
The surface of the region embedded in the SG cover insulating crotch 18 has a plasma oxide film (aluminum oxide film) 12.
A bipolar IC of the present invention having wiring, that is, an At output wiring 14, an At base wiring @13, an At emitter wiring, an At contact wiring, etc. (not shown), is swept.
なお上記第１の方法に於てプラズマ遮蔽膜は耐熱性を特
に必要としないので、レジスト等の有機物質で形成して
も良い。又第２の方法に於けるプラズマ遮蔽膜は耐熱性
が必要で、前記多結晶Ｓｔ膜以外に窒化シリコン（Ｓｉ
ｓＮ４）膜等が適している。Note that in the first method, the plasma shielding film does not particularly require heat resistance, so it may be formed of an organic material such as resist. In addition, the plasma shielding film in the second method requires heat resistance, and silicon nitride (Si) is used in addition to the polycrystalline St film.
sN4) membrane etc. are suitable.
（ｆ） 発明の詳細
な説明したように本発明によれば、りん珪酸ガラス絶Ｒ
ＭｊＣ埋込まれるアルミニウム配線は、該配線の表面に
形成される極めて強い耐薬品性を有するプラズマ酸化膜
、即ち酸化アルミニウム膜（こよって保護される。(f) As described in detail, according to the present invention, phosphosilicate glass
The aluminum wiring embedded in the MjC is protected by a plasma oxide film, that is, an aluminum oxide film, which has extremely strong chemical resistance and is formed on the surface of the wiring.
そのため吸湿によりりん珪酸ガラス絶Ｉ＃、ｌＩＩ中に
りん酸が生成した際にも、該りん酸によってアルミニウ
ム配線が腐食され、断線等を起すことがなくなるので、
半導体装置の信頼性は向上する。Therefore, even when phosphoric acid is generated in the phosphosilicate glasses I# and III due to moisture absorption, the phosphoric acid will not corrode the aluminum wiring and cause disconnection, etc.
The reliability of semiconductor devices improves.
なお本発明はＭＩＳ型の半導体装置にも適用される。又
前述したように多層配線構造にも適用できる。Note that the present invention is also applied to MIS type semiconductor devices. Further, as described above, it can also be applied to a multilayer wiring structure.
第１図は本発明の構造を有する半導体装置に於ける一実
施例の要部断面図、第２図（イ）乃至（ホ）は本発明の
方法の一実施例に於ける工程断面図１、第３図（イ）、
（ロ）は本発明の方法の他の一実施例に於ける工程断面
図である。
図に於て、１０は下層絶縁膜、１２はプラズマ酸化膜（
酸化アルミニウムｗＡ）、１．３＋２アルミニウＡ・ベ
ース配、１１．１４はアルミニウム出力配線、１４′は
配線接続パッド、１５はアルミニウム・エミッタ配線、
１６はアルミニウムーコレクタ配線、１７は配線接続窓
、１８はりん珪酸ガラス・カバー絶縁膜、１９は多結晶
シリコン膜、２０はエツチング窓、２１はレジス）ｌｌ
を示す。FIG. 1 is a sectional view of essential parts of an embodiment of a semiconductor device having the structure of the present invention, and FIGS. 2(A) to (E) are process sectional views 1 of an embodiment of the method of the present invention. , Figure 3 (a),
(B) is a process sectional view in another embodiment of the method of the present invention. In the figure, 10 is a lower insulating film, 12 is a plasma oxide film (
Aluminum oxide wA), 1.3+2 aluminum A base wiring, 11.14 is aluminum output wiring, 14' is wiring connection pad, 15 is aluminum emitter wiring,
16 is an aluminum collector wiring, 17 is a wiring connection window, 18 is a phosphosilicate glass cover insulating film, 19 is a polycrystalline silicon film, 20 is an etching window, 21 is a resist)
shows.
Claims (1)
酸化アルミニウム膜が選択的裔こ形成されたアルミニウ
ム配線が、該配線の配線接続パッド部上ｌこ配線接続窓
を有するりん珪酸ガラス絶縁膜に埋込まれてなることを
特徴とする半導体装置。 ２、アルミニウム配線の配線接続パッド上をプラズマ遮
蔽膜で選択的ｌこ覆りてプラズマ酸化処理を行い、該ア
ルミニウム配線の表出面上ｆこ選択的に酸化アルミニウ
ム膜を形成し、前記プラズマ遮蔽膜を除去した後、該ア
ルミニウム配線形成面上に、該配線の配線接続パッド部
上−こ配線接続窓を有するりん珪酸ガラス絶＃膜を形成
する工程を有することを特徴とする半導体装置の製造方
法。 ３、アルミニウム配線の配線接続パッド上を、耐熱性を
有するプラズマ遮蔽膜で選択的に覆ってプラズマ酸化処
理を行い、該アルミニウム配線の表出面上に選択的に酸
化アルミニウム膜を形成した後、該アルミニウム配線形
成面上にりん珪酸ガラス絶縁膜を形成し、該りん珪酸ガ
ラス股に於ける前記アルミニウム配線の配線接続パッド
上ｔこ配線接続窓内に前記アルミニウム配線の配線接続
パッド部を表出せしめる工程を有することを特徴とする
半導体装置の製造方法。[Scope of Claims] 1. An aluminum wiring on which an aluminum oxide film is selectively formed by plasma oxidation on the surface other than the wiring connection pad portion is a phosphor layer having a wiring connection window on the wiring connection pad portion of the wiring. A semiconductor device characterized by being embedded in a silicate glass insulating film. 2. Selectively cover the wiring connection pad of the aluminum wiring with a plasma shielding film and perform plasma oxidation treatment, selectively form an aluminum oxide film on the exposed surface of the aluminum wiring, and remove the plasma shielding film. A method for manufacturing a semiconductor device, comprising the step of: forming a phosphosilicate glass insulation film having a wiring connection window over the wiring connection pad portion of the wiring on the aluminum wiring formation surface after removing the aluminum wiring. . 3. After selectively covering the wiring connection pad of the aluminum wiring with a heat-resistant plasma shielding film and performing plasma oxidation treatment to selectively form an aluminum oxide film on the exposed surface of the aluminum wiring, A phosphosilicate glass insulating film is formed on the aluminum wiring formation surface, and the wiring connection pad portion of the aluminum wiring is exposed within the wiring connection window on the wiring connection pad of the aluminum wiring in the phosphosilicate glass crotch. 1. A method for manufacturing a semiconductor device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15150682A JPS5941853A (en) | 1982-08-31 | 1982-08-31 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15150682A JPS5941853A (en) | 1982-08-31 | 1982-08-31 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5941853A true JPS5941853A (en) | 1984-03-08 |
Family
ID=15519993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15150682A Pending JPS5941853A (en) | 1982-08-31 | 1982-08-31 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5941853A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61146882A (en) * | 1984-12-17 | 1986-07-04 | Dynic Corp | Decorative sheet |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5227387A (en) * | 1975-08-27 | 1977-03-01 | Hitachi Ltd | Forming system of multi-layer wiring |
| JPS54134991A (en) * | 1978-04-12 | 1979-10-19 | Kyushu Nippon Electric | Method of forming multilayer wiring of electronic part |
| JPS57120334A (en) * | 1981-01-17 | 1982-07-27 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1982
- 1982-08-31 JP JP15150682A patent/JPS5941853A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5227387A (en) * | 1975-08-27 | 1977-03-01 | Hitachi Ltd | Forming system of multi-layer wiring |
| JPS54134991A (en) * | 1978-04-12 | 1979-10-19 | Kyushu Nippon Electric | Method of forming multilayer wiring of electronic part |
| JPS57120334A (en) * | 1981-01-17 | 1982-07-27 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61146882A (en) * | 1984-12-17 | 1986-07-04 | Dynic Corp | Decorative sheet |
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