JPS5840942U - analog digital converter - Google Patents
analog digital converterInfo
- Publication number
- JPS5840942U JPS5840942U JP13541181U JP13541181U JPS5840942U JP S5840942 U JPS5840942 U JP S5840942U JP 13541181 U JP13541181 U JP 13541181U JP 13541181 U JP13541181 U JP 13541181U JP S5840942 U JPS5840942 U JP S5840942U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- power supply
- supply voltage
- analog
- digital converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図はAD変換器の概要を示すブロック図、第2図お
よび第5図は第1図の動作説明用の波形図およびグラフ
、第3図および第4図は第1図の要部を説明する回路図
、第6図は第1図の電源回路を示す回路図、第7図はそ
の特性図、第8図および第9図は第6図で生じる問題の
説明図、第10図および第11図は本考案の原理を示す
特性図および1172図、第12図は本考案の実施例を
示す回路図である。
図面で■。0は電源電圧、VREIi”は基準電圧、V
inは入力電圧、C)lはキャパシタ、IR−よ定電流
、VBはセンサ電源電圧、T□EF、 Tin、 TS
は放電時間、Q3. R1,R2,、I)、、 I)2
. op3はVRい+ VBの制御回路である。
第4図
第12図Figure 1 is a block diagram showing an overview of the AD converter, Figures 2 and 5 are waveform diagrams and graphs for explaining the operation of Figure 1, and Figures 3 and 4 are main parts of Figure 1. 6 is a circuit diagram showing the power supply circuit of FIG. 1, FIG. 7 is a characteristic diagram thereof, FIGS. 8 and 9 are explanatory diagrams of problems occurring in FIG. 6, and FIGS. FIG. 11 is a characteristic diagram showing the principle of the present invention, and FIG. 1172 and FIG. 12 are circuit diagrams showing an embodiment of the present invention. ■ In the drawing. 0 is the power supply voltage, VREIi'' is the reference voltage, V
in is the input voltage, C)l is the capacitor, IR- is the constant current, VB is the sensor power supply voltage, T□EF, Tin, TS
is the discharge time, Q3. R1, R2,, I),, I)2
.. op3 is a control circuit for VR+VB. Figure 4 Figure 12
Claims (1)
け、キャパシタを充電し次いで該電源電圧および基準電
圧で定まる定電流で放電させてその放電時間から入力ア
ナログ電圧のデジタル値を求めるシングルスロープ型の
アナログデジタル変換器において、電源電圧が一定値を
保持できない低電圧範囲では、前記基準電圧は電源電圧
と共に低下させそしてセンサの電源電圧はなお可及的に
一定に保持する回路を設けたことを特徴とするアナログ
デジタル変換回路。A single-slope type that receives a power supply voltage, a reference voltage, and an input voltage from a sensor, charges a capacitor, then discharges it with a constant current determined by the power supply voltage and reference voltage, and calculates the digital value of the input analog voltage from the discharge time. In the analog-to-digital converter, in a low voltage range where the power supply voltage cannot be maintained at a constant value, the reference voltage is lowered along with the power supply voltage, and a circuit is provided to maintain the power supply voltage of the sensor as constant as possible. Analog-to-digital conversion circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13541181U JPS5840942U (en) | 1981-09-11 | 1981-09-11 | analog digital converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13541181U JPS5840942U (en) | 1981-09-11 | 1981-09-11 | analog digital converter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5840942U true JPS5840942U (en) | 1983-03-17 |
JPS6320190Y2 JPS6320190Y2 (en) | 1988-06-06 |
Family
ID=29928780
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13541181U Granted JPS5840942U (en) | 1981-09-11 | 1981-09-11 | analog digital converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5840942U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60150832U (en) * | 1984-03-15 | 1985-10-07 | 三洋電機株式会社 | A/D conversion circuit |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4883674B2 (en) * | 2006-01-05 | 2012-02-22 | 株式会社山武 | Receiver amplifier |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5233803U (en) * | 1975-09-01 | 1977-03-10 | ||
JPS547262A (en) * | 1977-06-20 | 1979-01-19 | Nippon Soken | Ad converter |
-
1981
- 1981-09-11 JP JP13541181U patent/JPS5840942U/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5233803U (en) * | 1975-09-01 | 1977-03-10 | ||
JPS547262A (en) * | 1977-06-20 | 1979-01-19 | Nippon Soken | Ad converter |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60150832U (en) * | 1984-03-15 | 1985-10-07 | 三洋電機株式会社 | A/D conversion circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6320190Y2 (en) | 1988-06-06 |
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