JPS5835931A - Manufacture of wafer and semiconductor device - Google Patents
Manufacture of wafer and semiconductor deviceInfo
- Publication number
- JPS5835931A JPS5835931A JP13407981A JP13407981A JPS5835931A JP S5835931 A JPS5835931 A JP S5835931A JP 13407981 A JP13407981 A JP 13407981A JP 13407981 A JP13407981 A JP 13407981A JP S5835931 A JPS5835931 A JP S5835931A
- Authority
- JP
- Japan
- Prior art keywords
- defect
- substrate
- wafer
- surface layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 230000007547 defect Effects 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000002344 surface layer Substances 0.000 claims abstract description 19
- 238000010894 electron beam technology Methods 0.000 claims abstract description 9
- 238000000137 annealing Methods 0.000 claims description 8
- 238000010301 surface-oxidation reaction Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims 1
- 238000001259 photo etching Methods 0.000 claims 1
- 239000013078 crystal Substances 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 abstract description 7
- 239000001301 oxygen Substances 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 239000006104 solid solution Substances 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract description 2
- 238000005498 polishing Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000008021 deposition Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 25
- 238000005247 gettering Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000001590 oxidative effect Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 239000002244 precipitate Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004397 blinking Effects 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 210000001161 mammalian embryo Anatomy 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000035936 sexual power Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は牛導体つエーノ・訃よび半導体装置の製造方法
Ｋ１１ｌする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.
半導体装置の特性劣化、特性同上を図るためには、ＰＭ
接合を結晶欠陥のない無欠陥領域に形成することが要求
ちれる。In order to improve the characteristics of semiconductor devices, PM
It is required that the junction be formed in a defect-free region free of crystal defects.
しかし、現在の結晶育成技術では、微小欠陥フリーの結
晶は実現できないため、デバイス（半導体装置）の製造
プロセスでは種々の欠陥制御技術（ゲッタリング）が施
もれている。七の代表的なものにイントリンシック・ゲ
ッタリング、裏面ひずみ等がある。無欠陥領域にＰＮ接
合を形成する技術としてのイントリンシック・ゲッタリ
ングは８１１１図に示すように、シリコンウェーハ１ｔ
−非酸化性雰囲気でアニール（〜１２００ Ｃ） Ｌ、
、結晶内のＩＩＸ會外方拡散させ、表面層に無欠陥領域
２を形成する一方、続く低温アニール（〜８００℃）で
微小欠陥３ｔバルク４円に生せしめ、この欠陥によって
表面層の不純物會ゲッターする方法でめる。またその他
に、ウェーハ畳面にひずみ會残丁方法、あるいけ裏面に
高濃度リン拡散を行なり。However, with current crystal growth techniques, crystals free of minute defects cannot be realized, so various defect control techniques (gettering) are applied in the manufacturing process of devices (semiconductor devices). Typical examples of the seven include intrinsic gettering and backside distortion. Intrinsic gettering is a technology for forming PN junctions in defect-free areas, as shown in Figure 8111.
- Annealed in non-oxidizing atmosphere (~1200 C) L,
, IIX particles in the crystal are diffused outward to form a defect-free region 2 in the surface layer, while subsequent low-temperature annealing (~800°C) generates micro defects in 3t bulk 4 circles, and these defects cause impurity groups in the surface layer. Get it using the getter method. In addition, we also applied a strain-retaining method to the wafer surface and high-concentration phosphorus diffusion to the back surface of the wafer.
七のさい発生するミスフィツト転位によってゲッタリン
グ効果音あげる方法などがある。There is a method to create a gettering sound effect by using the misfit dislocation that occurs at the time of seven.
しかし、前記イントリンシック・ゲッタリングは高温（
、〜１２００Ｃ）で数時間から時１ｃは十数時間の、賂
らＫ、低温（〜５ｏｏｃ）で数時間のアニールを必要と
し、極めて大喪で１１７生産性が低くコスト高となる。However, the intrinsic gettering is performed at high temperatures (
, ~1200C) for several hours to several tens of hours at low temperature (~1200C), which requires several hours of annealing at a low temperature (~5oC), resulting in extremely low productivity and high costs.
また、裏面ひずみ法では、ひずみｍ′ｆｔ−均一に入れ
ることが難しいこと、および、ひずみの部分で熱応力転
位が発生し易く新な欠陥の発生に繋るなどの１％ｔ１題
がある。In addition, the backside strain method has 1%t1 problems, such as the difficulty of uniformly introducing strain m'ft and the tendency for thermal stress dislocation to occur in strained areas, leading to the generation of new defects.
したがって、本発明の目的は、欠陥の無い表層部ｔ−肩
するウェーハを短時間に製造する方法および無欠陥領域
ＫＰＮ接合１に有する品質の亮い半導体装置の製造方法
を提供することＫめる。Therefore, an object of the present invention is to provide a method for manufacturing a defect-free surface layer wafer in a short time and a method for manufacturing a high-quality semiconductor device having a defect-free region KPN junction 1. .
このような目的を達成するために本発８Ａは、シリコン
半導体ウェーハ會表面酸化るるいは非酸化性雰囲気中で
アニールしたのち、またけヤの前に、大出力の電子−照
射、キセノンランプ照射（酸化膜のついてｂなり状態で
はレーザ照射が有効）を行ない、ウェーハの表面層（表
層ｆ＠Ｓ）６μｍの領域において、融解−再結晶化を生
ぜしめ、その場い結晶育成に起叩する微小欠陥（スワー
ル）や酸化のさし発生ずる［１欠陥、酸素析出物、転位
ループ等の結晶欠陥をシリコン母相に再固溶ぜしめ、再
結晶化領域を無欠陥領域とし、この領域にＰＮ接合を形
成することを特徴とする。In order to achieve this purpose, the present invention 8A uses high-output electron irradiation and xenon lamp irradiation after annealing the surface of a silicon semiconductor wafer in an oxidizing or non-oxidizing atmosphere, and before straddling it. (Laser irradiation is effective when the oxide film is in the state of b) to cause melting-recrystallization in a 6 μm region of the wafer surface layer (surface layer f@S) and stimulate in-situ crystal growth. Crystal defects such as micro defects (swirls) and oxidation are generated [1] Crystal defects such as defects, oxygen precipitates, and dislocation loops are redissolved in the silicon matrix, and the recrystallized region is made into a defect-free region. It is characterized by forming a PN junction.
以下、実施例により本発明ｔｅ明する。The present invention will be explained below with reference to Examples.
＃２図は本発明の一実施例による半導体装置の製造工程
を示すフローチャートである。半導体装置の製造におい
ては、まず、シリコン□単結晶を用意しｔ後、スライシ
ングして薄板（ウエーノＳ）とし、七の後、ラッピング
、ポリシング等を行なって鏡面ウェーハとする。一般に
はこれまでの作業工Ｓｔ−％にウェーハ製造工程Ａと呼
び、での後の作業工、ｔＭｋデバイス・プロセスＢと呼
んでいる。Figure #2 is a flowchart showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. In the manufacture of semiconductor devices, first a silicon single crystal is prepared, then sliced into thin plates (waeno S), and then subjected to lapping, polishing, etc. to form mirror-finished wafers. Generally, the previous work St-% is called wafer manufacturing process A, and the subsequent work is called tMk device process B.
デバイス・プロセスＢ＆Ｃ移ったウェーハ１は第３図に
示すように、熱酸化により表１１ｆｌを酸化（ａｉ（ｈ
ｊｌ［化）ネれる。つぎに、このウェーハ１は電子＊１
−照射される。電子ｗＪ照射は酸化膜（８１０ｍ膜）５
上に行なわれる。この結果、酸化膜５の下層のウエーノ
・１の表層Ｓは−［１に解、再結晶化が行なわれ、単時
間下で無欠ｗｉ４＠ｂｌ ２となる。As shown in FIG. 3, the wafer 1 transferred to the device process B&C has the table 11fl oxidized (ai (h) by thermal oxidation.
jl [to become] Next, this wafer 1 has an electron*1
-Irradiated. Electron wJ irradiation is performed on oxide film (810m film) 5
done above. As a result, the surface layer S of Ueno.1 below the oxide film 5 is dissolved into -[1, recrystallized, and becomes intact wi4@bl2 in a short period of time.
丁なわち、この方法では、シリコンウェー／ＳＬを熱処
理し、表面層の固溶酸素全外方の酸化膜５中に拡散せし
めたのち、極めて短時間（〜ｍθ以下）の照射によって
表面層数μｍの領域のみを融解−再結晶化さぞ、無欠陥
層を形成できる。いつ九ん、照射部分が融解するｔめ、
スワール等の前核段階（エンブリヨウ）のクラスターが
完全に消失してしまい、また外方拡散によって固溶＃累
濃度が減少しているので、続けて熱処理しても照射領域
には酸素の析出による欠陥形成か起こらない。In other words, in this method, the silicon wafer/SL is heat-treated and the solid solution oxygen in the surface layer is completely diffused into the outer oxide film 5, and then the number of surface layers is A defect-free layer can be formed by melting and recrystallizing only a μm region. At some point, the irradiated part will melt.
Clusters at the pre-nucleus stage (embryo) such as swirls have completely disappeared, and the cumulative solid solution # concentration has decreased due to outward diffusion, so even if heat treatment is continued, oxygen will precipitate in the irradiated area. No defect formation occurs.
また、短時間かつ局所加熱のため、基板内の特性は影響
もれない。Furthermore, since the heating is done locally and for a short time, the characteristics within the substrate are not affected.
そこで、この無欠陥領域に電気的に活性なＰＭ接合を通
常の拡散技術によって形成することによって、製造する
半導体装置の微小欠陥の存在による接合リーク不良は減
小あるいは防止できることに一＆す、半導体装置の特性
向上、信頼性、寿命の向上が図れる。この実施例の応用
可能な素子の一例としては、メモリ素子（６４にダイナ
ミックＲムＭ）や撮＊＊子（Ｍ Ｏ８Ｉｍａｇｅ Ｄｅ
ｖｉｃｅ ） ｉＥある。これらの素子は、結晶欠陥
の存在によって特性が劣化し易いからである。たとえば
、微／」１欠陥の存在のために生じる接合リークによる
不良としては、メモリ素子ではリフレッシュ不良として
現われ、撮ｇＩ素子としては白点不良となって現われる
。したがって、乙の実施行の適用により、これらの不良
発生は防止できる。なお、Ｖｂｅ工のプロセスは低温化
を志向してシ９、七の点でハ熱が加わらない電子−アニ
・−ル、また後記するレーザーアニール処理は有効でめ
る。Therefore, by forming an electrically active PM junction in this defect-free region using normal diffusion technology, it is possible to reduce or prevent junction leakage defects caused by the presence of micro defects in semiconductor devices to be manufactured. It is possible to improve the characteristics, reliability, and lifespan of the device. Examples of devices to which this embodiment can be applied include a memory device (dynamic RM M at 64) and a camera (MO8Image De
vice) There is iE. This is because the characteristics of these elements tend to deteriorate due to the presence of crystal defects. For example, a defect due to a junction leak caused by the presence of a micro/''1 defect appears as a refresh defect in a memory element, and as a white spot defect in a gI element. Therefore, by applying the implementation procedures of Party B, these defects can be prevented from occurring. Incidentally, the Vbe process is aimed at lowering the temperature, and in points (9) and (7), electron annealing, which does not apply heat, and laser annealing, which will be described later, are effective.
ｔた、この実１ｓ例において、電子騨照射後のデバイス
・プロセスでＭｆ熱処理を行なうことによって、ウェー
７１の結晶内部に含まれる酸素の外方拡散およびバルク
欠陥の核発生を促進することｉ＝できる。たとえば、酸
素の外方拡散として、１２００℃の非酸化性雰囲気中で
のアニール、バルク４内に結晶欠陥の核を発生させ、イ
ントリンシック−ゲッタリング効果を期待できる方法と
しては、８００℃程度の７ニールが考えられる。この結
果、ウェーハの表層部には欠陥のなり無欠陥領域２１に
形作ることができる。In addition, in this practical example, Mf heat treatment is performed in the device process after electron irradiation to promote out-diffusion of oxygen contained within the crystal of the wafer 71 and nucleation of bulk defects. can. For example, annealing at 1200°C in a non-oxidizing atmosphere is a method for outward diffusion of oxygen, which generates crystal defect nuclei in the bulk 4, and is expected to produce an intrinsic gettering effect. 7 Neil is possible. As a result, the surface layer of the wafer can be formed into a defect-free region 21 with no defects.
なシ１本発明は前記実施例に限定されない。友とえば、
ｔｌＩＡ４図１８１のフローチャートで示すようＫ、表
面酸化工程と電子！ＩＳ射工程との間に高温アニール処
理ｔ−２〜２０時間行なめ、ウェーハの表層部の無欠陥
化を図るようにしてもよい。1. The present invention is not limited to the above embodiments. For example, a friend
tlIA4 As shown in the flowchart in Figure 181, K, surface oxidation process and electron! A high-temperature annealing treatment for t-2 to 20 hours may be performed between the IS irradiation step and the surface layer of the wafer to be defect-free.
まｔ、第４図１ｂｌ Ｋ示すように、ウェーハの表面酸
化工程の前にレーザー照射をウェーハの表層部（数ｐｍ
）？行ない、ウェーハの表層部の無欠陥領域化を図って
もよい。この場合、レーザーはパルスレーザ−を用い、
出力はｉｏｏ〜１０ＵＯＭｆで行なうとよい。また、レ
ーザー照射に変えて電子線照射によって行なってもよい
。Also, as shown in Figure 4, 1blK, laser irradiation is applied to the surface layer of the wafer (several pm) before the wafer surface oxidation process.
)? Alternatively, the surface layer of the wafer may be made into a defect-free region. In this case, a pulsed laser is used as the laser,
The output is preferably ioo to 10UOMf. Further, instead of laser irradiation, electron beam irradiation may be used.
場らに、本発明はウェーハの全！５！面を行なうように
丁れば、どのような半導体装置の製造にも適する。した
がって２ウエーハ供給という観点からすれば、鏡面ウェ
ーハの全表面にレーザ−７ニールあるいは電子線アニー
ル１行なって、ウェーハの表層部の無欠陥化を図って出
荷丁ればよい。また、デバイスプロセスの観点から丁れ
ば、レーザ照射、電子線照射はＰＭ接合を形成するアク
ティブ領域のみｔ無欠陥仕丁ればよく、ウェーハ全表面
の無欠陥化処理は無駄が多い。そこで２ウエーハの必要
部分にのみ、レーザー光るるいは電子線を照射して生−
性の向上を図るとよい。仁の場合。In particular, the present invention applies to all wafers! 5! It is suitable for manufacturing any kind of semiconductor device if it is folded so that the surfaces are aligned. Therefore, from the viewpoint of supplying two wafers, it is sufficient to perform seven laser annealing or one electron beam annealing on the entire surface of the mirror-finished wafer to make the surface layer part of the wafer defect-free before shipping. Further, from the viewpoint of device processing, laser irradiation and electron beam irradiation only need to be performed on the active area forming the PM junction to ensure no defects, and it is wasteful to treat the entire wafer surface to be defect-free. Therefore, only the necessary parts of the two wafers are irradiated with laser light or electron beams.
It is a good idea to improve your sexual performance. In the case of Jin.
１スク會用いてもまた、電子線、レーザー光の走査時の
点滅によって行なってもよい。It may be carried out by using one screen or by blinking during scanning with an electron beam or laser beam.
以上のように、本発明によれば、欠陥の無い表層部′を
肩するウェーハを短時間に製造することができるととも
に、無欠陥領域［ＰＭ接合を形成できることから、特性
が良好で寿命、信頼度が高い半導体装置を製造すること
ができる。As described above, according to the present invention, a wafer with a defect-free surface layer can be manufactured in a short time, and since a defect-free area [PM junction] can be formed, the wafer has good characteristics, long life, and reliability. It is possible to manufacture semiconductor devices with high performance.
＄１図は従来のウェーハの断面構造を示ア概念図、第２
図は本発明の一実施例による半導体装置製造工種の一部
を示すフローチャート、ｌｌＬａ図は同じくウェー７１
の断面構造の概念図、隼４図−２ｔｉｌｌは他の実施例
によるフローチャートである。
１−・・ウエーノ・、２・・・無欠陥領域、３・・・微
小欠陥、４・・・バルク、５・・・８１（ｈｌ！。
第 １ 図 第 ２
図ＩFigure 1 is a conceptual diagram showing the cross-sectional structure of a conventional wafer.
The figure is a flowchart showing a part of the semiconductor device manufacturing process according to an embodiment of the present invention, and the figure llLa is the same way 71.
A conceptual diagram of the cross-sectional structure of , and Figure 4-2till is a flowchart according to another embodiment. 1-...Weno..., 2...Defect-free area, 3...Minute defect, 4...Bulk, 5...81 (hl!. Fig. 1 Fig. 2
Figure I
Claims (1)
レーザー元金照射して、所望表層部′ｋＭ解。 再結晶化姑ぜ、再結晶化領域を無欠陥領域とすることを
％値とするウェー７１の製造方法。 ２、 ＠面研摩したウェーハの主面に表面酸化を施こ
シを後に、フォトエツチングによってマスクパターン全
形成する工程？Ｉ−有する半導体装置の製造方法におい
て、前記表面酸化工程の前または後にウェーハの主面の
所望領域に、電子線、レーザー元ｔ−照射して、所望表
層部全融解、再結晶化さぞ、再顯晶化領域ヲ焦久陥領域
とするとともに、半導体装置製造時にはこの無欠陥領域
にＰＮ接合を形成することｔ％徴とする半導体装置の製
造方法。 ３、前記無欠陥領域形成後に、アニールを行ない、無欠
陥領域の下層の母材中に慎小欠陥を形ｇ、ｊること′に
特徴とする特許−求の範囲＃２項記載の半導体装置の製
造方法。[Claims] 1. Electron beam,
Irradiate the laser source to obtain the desired surface layer 'kM solution. A method for manufacturing a wafer 71 in which the percentage value is that the recrystallized region is defect-free. 2. The process of performing surface oxidation on the main surface of the polished wafer and then forming the entire mask pattern by photoetching? In the method for manufacturing a semiconductor device having I-, a desired region of the main surface of the wafer is irradiated with an electron beam or a laser source before or after the surface oxidation step to completely melt the desired surface layer, recrystallize it, and re-crystallize it. A method for manufacturing a semiconductor device, in which a crystallized region is made into a focused region, and a PN junction is formed in this defect-free region during semiconductor device manufacturing. 3. The semiconductor device according to claim #2 of the patent, characterized in that after the defect-free region is formed, annealing is performed to form small defects g, j in the base material below the defect-free region. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13407981A JPS5835931A (en) | 1981-08-28 | 1981-08-28 | Manufacture of wafer and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13407981A JPS5835931A (en) | 1981-08-28 | 1981-08-28 | Manufacture of wafer and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5835931A true JPS5835931A (en) | 1983-03-02 |
Family
ID=15119903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13407981A Pending JPS5835931A (en) | 1981-08-28 | 1981-08-28 | Manufacture of wafer and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5835931A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59217333A (en) * | 1983-05-26 | 1984-12-07 | Toshiba Corp | Treating method of semiconductor wafer |
| JPS6042838A (en) * | 1983-08-19 | 1985-03-07 | Toshiba Corp | Method for processing semiconductor wafer |
| JPS6236481A (en) * | 1985-07-05 | 1987-02-17 | ザ ダウ ケミカル カンパニ− | Laminar metal hydroxide-clay adduct mixture as thickener of water and hydrophilic fluid |
-
1981
- 1981-08-28 JP JP13407981A patent/JPS5835931A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59217333A (en) * | 1983-05-26 | 1984-12-07 | Toshiba Corp | Treating method of semiconductor wafer |
| JPS6042838A (en) * | 1983-08-19 | 1985-03-07 | Toshiba Corp | Method for processing semiconductor wafer |
| JPS6236481A (en) * | 1985-07-05 | 1987-02-17 | ザ ダウ ケミカル カンパニ− | Laminar metal hydroxide-clay adduct mixture as thickener of water and hydrophilic fluid |
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