JPS5823023B2 - Reception data signal generation circuit - Google Patents
Reception data signal generation circuitInfo
- Publication number
- JPS5823023B2 JPS5823023B2 JP13408677A JP13408677A JPS5823023B2 JP S5823023 B2 JPS5823023 B2 JP S5823023B2 JP 13408677 A JP13408677 A JP 13408677A JP 13408677 A JP13408677 A JP 13408677A JP S5823023 B2 JPS5823023 B2 JP S5823023B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- carrier
- data signal
- received data
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
- H04L27/06—Demodulator circuits; Receiver circuits
- H04L27/066—Carrier recovery circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Communication Control (AREA)
- Noise Elimination (AREA)
- Circuits Of Receivers In General (AREA)
Description
【発明の詳細な説明】
本発明はデータ通信用の変復調装置における受信データ
信号作成回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a received data signal generation circuit in a modulation/demodulation device for data communications.
従来、データ通信用の変復調装置においては、第１図の
ブロック図で示すような受信データ信号作成回路を用い
て電子計算機などに供給する受信データを作成している
。2. Description of the Related Art Conventionally, in a data communication modulation/demodulation device, received data to be supplied to an electronic computer or the like is created using a received data signal creating circuit as shown in the block diagram of FIG.
すなわち、受信入力端子１からの変調波信号を受信回路
２で受信した後、この変調波信号をキャリア検出回路３
と復調回路４に送り、キャリア検出回路３のキャリア検
出信号（・１・・レベル）と復調回路４によって変調波
信号から取り出された直流２進値信号すなわち受信デー
タ信号とを論理積回路５で論理積をとり、この出力を受
信データ信号としている。That is, after receiving the modulated wave signal from the receiving input terminal 1 at the receiving circuit 2, this modulated wave signal is sent to the carrier detecting circuit 3.
is sent to the demodulation circuit 4, and the carrier detection signal (.1 level) of the carrier detection circuit 3 and the DC binary value signal extracted from the modulated wave signal by the demodulation circuit 4, that is, the received data signal, are combined by the AND circuit 5. A logical AND is performed, and the output is used as a received data signal.
ところが、前記キャリア検出回路３から出力されるキャ
リア検出信号は、第２図すにタイムチャートとして示す
ように、受信入力端子１に第２図ａに示すような変調波
信号を受信してから・１・・レベルのキャリア検出信号
を送出するまでに一定のキャリア検出時間ｔ１を有して
いる。However, as shown in the time chart of FIG. 2, the carrier detection signal output from the carrier detection circuit 3 is generated after receiving the modulated wave signal shown in FIG. 2a at the receiving input terminal 1. A certain carrier detection time t1 is required until a carrier detection signal of level 1 is sent out.
また、受信入力端子１に受信された変調波信号が停止さ
れてから（詳しくは、受信入力端子に与えられる変調波
信号のレベルが規定レベル以下になってからである。Also, after the modulated wave signal received at the reception input terminal 1 is stopped (more specifically, after the level of the modulated wave signal applied to the reception input terminal becomes below the specified level).
）キャリア断信号（・０・レベル）を送出するまでに一
定のキャリア断検出時間ｔ２を有している。) It has a certain carrier disconnection detection time t2 before sending out the carrier disconnection signal (.0 level).
このキャリア断検出時間ｔ２は、例えば１２００ｂ／ｓ
変調装置においては、７〜４０ｍ５の範囲に定められる
のが一般的である。This carrier disconnection detection time t2 is, for example, 1200 b/s.
In modulators, the width is generally set in the range of 7 to 40 m5.
データ通信において、データキャラクタ、を７単位符号
とし、調歩同期方式で伝送する場合、スタートビット、
ストップビットおよびパリティビットを付加して１キヤ
ラクタ１０ビツト構成とした時の１キャラクタ時間長は
約８．３ ｍｓとなるので、１２時間が１キャラクタ時
間を越えることがしばしば発生する。In data communication, when the data character is a 7-unit code and is transmitted using the asynchronous method, the start bit,
When a stop bit and a parity bit are added to form one character with 10 bits, the time length of one character is about 8.3 ms, so 12 hours often exceeds one character time.
従って、キャリア断検出時間ｔ２の期間に第２図ａのＮ
で示すような雑音が受信入力端子１に加わった場合、こ
の雑音Ｎは復調回路４で復調され（第２図Ｃの破線）、
キャリア検出信号との論理積がとられ、第２図Ｃの破線
部分で示すような受信データとして送出されてしまう。Therefore, during the carrier disconnection detection time t2, N in FIG.
When noise as shown in is added to the reception input terminal 1, this noise N is demodulated by the demodulation circuit 4 (dashed line in FIG. 2C),
A logical product with the carrier detection signal is taken, and the received data is sent out as shown by the broken line in FIG. 2C.
この雑音は、回線の状態によってしばしば発生し、とく
に、受信データ信号を電子計算機などに入力してデータ
処理する。This noise often occurs depending on the state of the line, and in particular, the received data signal is input to an electronic computer or the like for data processing.
場合、雑音による受信データ信号がたまたま伝送制御キ
ャラクタの５ＴＸ（５ｔａｒｔ ｏｆ Ｔｅｘｔ ）
と同じ信号になった時には、次に来るべきデータのＳ
ＴＸと見なして動作するため、システム上の誤動作を発
生させ、極めて不都合なものになっていた。In this case, the received data signal due to noise happens to be the transmission control character 5TX (5tart of Text).
When the signal becomes the same as that of the next data S
Since it operates as if it were a TX, it causes malfunctions in the system, which is extremely inconvenient.
一方、第１図のキャリア検出回路３の出力信号は、電子
計算機等とデータ端末装置等とのデータリンクの確立を
監視するのに使用されているため、キャリア断検出時間
ｔ２を単純に短縮することはできない。On the other hand, since the output signal of the carrier detection circuit 3 in FIG. 1 is used to monitor the establishment of a data link between an electronic computer, etc. and a data terminal device, etc., the carrier disconnection detection time t2 can be simply shortened. It is not possible.
すなわち、キャリア断検出時間ｔ２を小さくすると、デ
ータリンク確立中に回線の瞬断や雑音が発生して短時間
受信入力が瞬断した場合にもキャリア断検出信号を送出
することになり、短時間の受信入力断をデータリンクの
途中開放と判断することになって不都合が生じる。In other words, if the carrier disconnection detection time t2 is made smaller, the carrier disconnection detection signal will be sent even if the reception input is momentarily interrupted for a short time due to a momentary line disconnection or noise that occurs during data link establishment. An inconvenience arises because a disconnection of the reception input is determined to be an opening of the data link.
つまり、どのような不都合かというと、キャリア検出回
路３が短時間の受信入力断をキャリア断と判定しないな
らば、短時間の受信入力断に相当する部分のデータを再
送要求し、再送を受けることによって正常なデータ伝送
が達成される。In other words, what kind of inconvenience is this? If the carrier detection circuit 3 does not determine that a short-term loss of reception input is a loss of carrier, it requests retransmission of the portion of data corresponding to the short-time loss of reception input and receives the retransmission. This achieves normal data transmission.
しかし、キャリア検出回路３が短時間の受信入力断をキ
ャリア断と判定してしまえば、データリンクの途中解放
を意味するため、単に再送要求および再送に伴う手順だ
けでなく、データリンクの途中解放によるシステムの異
常状態のリセット、新たなデータリンクの確立等の手順
を完了させたのち改めてデータ送受を行なわなければな
らない。However, if the carrier detection circuit 3 determines that a short-time loss of reception input is a carrier loss, it means that the data link is released midway. After completing procedures such as resetting the abnormal state of the system and establishing a new data link, data transmission and reception must be performed again.
従って、このよ−うな不都合が発生するため、単純にキ
ャリア断検出時間ｔ２を１キヤラクタ長以下に短縮して
前述したようなシステム上の誤動作を防止することは適
切でない。Therefore, since such inconvenience occurs, it is not appropriate to simply shorten the carrier disconnection detection time t2 to one character length or less to prevent the above-described system malfunction.
このため、従来における雑音によるシステムの誤動作対
策としては、電子計算機ある、いはデータ末端装置側で
ソフトウェア的あるいはハードウェア的に対策を実施す
る必要があった。For this reason, conventional countermeasures against system malfunctions due to noise have required implementing software or hardware measures on the electronic computer or data end device side.
従って、本発明の目的は、キャリア断検出時間内におい
て受信入力端子に加わった雑音が受信データ信号として
送出されないような受信データ信Ｊ号作成回路を提供す
ることにある。Therefore, an object of the present invention is to provide a received data signal J signal generating circuit in which noise added to the receiving input terminal during the carrier disconnection detection time is not sent out as the received data signal.
このような目的を達成するために、本発明による受信デ
ータ信号作成回路は、復調回路出力とキャリア検出回路
出力との論理積をとって受信データ信号を作成している
論理積回路に、新たに設け・た前記キャリア検出回路の
キャリア断検出時間よりも短時間でキャリア断を検出す
るキャリア検出回路の出力を加えて論理積をとり、キャ
リア断検出時間内において受信入力端子に加わった雑音
が受信データ信号として送出されないようにしたもので
ある。In order to achieve such an object, the received data signal generation circuit according to the present invention newly adds a new function to the AND circuit that generates the received data signal by taking the AND of the output of the demodulation circuit and the output of the carrier detection circuit. The output of the carrier detection circuit that detects carrier disconnection in a shorter time than the carrier disconnection detection time of the provided carrier detection circuit is added and logically multiplied to determine whether the noise added to the reception input terminal within the carrier disconnection detection time is received. This is so that it is not sent out as a data signal.
以下、図面を用いて本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail using the drawings.
第３図は本発明による受信データ信号作成回路の一実施
例を示すブロック図であり、第１図と同一部分は同一記
号を用いている。FIG. 3 is a block diagram showing an embodiment of the received data signal generating circuit according to the present invention, and the same parts as in FIG. 1 are denoted by the same symbols.
同図において、第１図と異なる点は、キャリア検出回路
３のキャリア断検出時間ｔ２よりも短時間のキャリア断
検出時間ｔ４を有する第２のキャリア検出回路６を；新
たに設け、この出力を論理積回路５ａに加えた点にある
。In this figure, the difference from FIG. 1 is that a second carrier detection circuit 6 is newly provided and has a carrier disconnection detection time t4 shorter than the carrier disconnection detection time t2 of the carrier detection circuit 3; This is in addition to the AND circuit 5a.
このように構成された受信データ信号作成回路の動作を
第４図タイムチャートを用いて説明する。The operation of the received data signal generating circuit configured as described above will be explained using the time chart of FIG.
まず、第４図ａに示すような変調波信号が入力端子１に
加わると、この変調波信号は受信回路２で受信された後
、キャリア検出回路３、復調回路４やよび第２のキャリ
ア検出回路６に供給される。First, when a modulated wave signal as shown in FIG. It is supplied to circuit 6.
この時、キャリア検出回路３および復調回路４は、従来
と同様にして動作し、それぞれの出力は第４図Ｃおよび
ｄに示すようになる。At this time, the carrier detection circuit 3 and the demodulation circuit 4 operate in the same manner as in the conventional case, and their respective outputs become as shown in FIG. 4C and d.
一方、第２のキャリア検出回路６は、第４図すに示すよ
うにキャリア検出時間がｔ３、キャリア断検出時間がｔ
４として設定されており、キャリア検出回路３のそれと
はｔ １）ｔ ３ 、 ｊ ２）１４なる関係をもって
いる。On the other hand, the second carrier detection circuit 6 has a carrier detection time t3 and a carrier disconnection detection time t3, as shown in FIG.
4, and has a relationship with that of the carrier detection circuit 3 as follows: t 1) t 3 , j 2) 14.
なお、第２のキャリア検出回路６のキャリア断検出時間
ｔ４は、雑音による受信データが伝送制御キャラクタの
ＳＴＸを構成しない時間すなわち、ＳＴＸはＩＳＯコー
ドの場合、２進値信号で０Ｏ０００１０信号であるので
６ビツト長に相当する時間未満に設定されればよい、従
って、受信回路２から変調波信号が第２のキャリア検出
回路６に与えられると、その出力は第４図すに示すよう
になる。Note that the carrier disconnection detection time t4 of the second carrier detection circuit 6 is the time during which the received data due to noise does not constitute the transmission control character STX. It is sufficient to set the time to less than the time corresponding to the 6-bit length. Therefore, when the modulated wave signal is given from the receiving circuit 2 to the second carrier detecting circuit 6, its output becomes as shown in FIG.
この出力は論理積回路５ａに与えられているため、論理
積回路５ａから出力される受信データ信号出力は第４図
ｅに示すように雑音Ｎによる受信データ信号部分が取り
除かれたものになる。Since this output is given to the AND circuit 5a, the received data signal output from the AND circuit 5a has the received data signal portion due to the noise N removed, as shown in FIG. 4e.
このように本実施例によれば、雑音による受信データ信
号は復調回路４の出力には現われるが、論理積回路５ａ
の出力には現われない。According to this embodiment, the received data signal due to noise appears in the output of the demodulation circuit 4, but the received data signal due to noise appears in the output of the AND circuit 5a.
does not appear in the output.
このため、従来のように、電子計算機側あるいはデータ
端末装置側でソフトウェア的あるいはハードウェア的な
雑音対策を実施する必要はなくなる。Therefore, it is no longer necessary to implement software or hardware noise countermeasures on the computer side or the data terminal device side, as in the past.
なお、本実施例においては、キャリア検出回路３のキャ
リア断検出時間より短いキャリア断検出時間を有する第
２のキャリア検出回路６を独立して設けているが、第５
図に示すようにしてもよい。Note that in this embodiment, the second carrier detection circuit 6 having a carrier disconnection detection time shorter than the carrier disconnection detection time of the carrier detection circuit 3 is provided independently;
It may be configured as shown in the figure.
すなわち、第４図の第２のキャリア検出回路６と、この
出力によって作動し規定のキャリア検出時間ｔ１とキャ
リア断検出時間ｔ２を作成するタイマー回路７を設け、
復調回路４の出力、キャリア検出回路６の出力およびタ
イマー回路７の出力とを論理積回路５ａに接続してもよ
い。That is, a second carrier detection circuit 6 shown in FIG. 4 and a timer circuit 7 which is activated by this output and creates a prescribed carrier detection time t1 and carrier disconnection detection time t2 are provided.
The output of the demodulation circuit 4, the output of the carrier detection circuit 6, and the output of the timer circuit 7 may be connected to the AND circuit 5a.
つまり、キャリア検出回路６とタイマー回路７とで第３
図ある。In other words, the carrier detection circuit 6 and the timer circuit 7
There is a diagram.
いは第１図のキャリア検出回路３と同一機能になる。Otherwise, it has the same function as the carrier detection circuit 3 shown in FIG.
以上説明したように、本発明によれば、キャリア断検出
時間内に発生する雑音に起因する受信データ信号の送出
を禁止することができる。As described above, according to the present invention, it is possible to prohibit the transmission of a received data signal due to noise generated within the carrier disconnection detection time.
このた」め、変復調装置に接続される電子計算機あるい
はデータ端末装置は、複雑な雑音対策を行う必要がなく
なり、機能の簡易化を計る上で極めて有効なものとなる
。Therefore, the electronic computer or data terminal device connected to the modulation/demodulation device does not need to take complicated noise countermeasures, and is extremely effective in simplifying its functions.
また、本発明による受信データ信号作成回路は、従来回
路に第２のキャリア検出回路を付加するだけであるため
、実施が極めて容易である。Further, the received data signal generating circuit according to the present invention is extremely easy to implement because it only requires adding a second carrier detection circuit to the conventional circuit.
さらに、データ通信システムの信頼性を高める上で極め
て有効なものとなる。Furthermore, it is extremely effective in increasing the reliability of data communication systems.
第１図は従来の受信データ信号作成回路のブロック図、
第２図は第１図に示す回路の動作を説明するためのタイ
ムチャート、第３図は本発明による受信データ信号作成
回路の一実施例を示すブロック図、第４図は第３図に示
す回路の動作を説明するためのタイムチャート、第５図
は本発明による受信データ信号作成回路の他の実施例を
示すブロック図である。
１・・・・・・受信入力端子、２・・・・・・受信回路
、３・・・・・・キャリア検出回路、４・・・・・・復
調回路、５，５ａ・・・・・・論理積回路、６・・・・
・・第２のキャリア検出回路、７・・・・・・タイマー
回路。Figure 1 is a block diagram of a conventional received data signal generation circuit.
FIG. 2 is a time chart for explaining the operation of the circuit shown in FIG. 1, FIG. 3 is a block diagram showing an embodiment of the received data signal generating circuit according to the present invention, and FIG. 4 is shown in FIG. A time chart for explaining the operation of the circuit, and FIG. 5 is a block diagram showing another embodiment of the received data signal generating circuit according to the present invention. 1... Reception input terminal, 2... Receiving circuit, 3... Carrier detection circuit, 4... Demodulation circuit, 5, 5a...・Logic product circuit, 6...
...Second carrier detection circuit, 7...Timer circuit.
Claims (1)
路によって論理積をとり受信データ信号出力としている
データ通信用変復調装置の受信データ信号作成回路にお
いて、前記キャリア検出回路のキャリア断検出時間より
も短いキャリア断検出時間を有する第２のキャリア検出
回路を設け、受信データ信号の作成を該第２のキャリア
検出回路出力をも含めて論理積をとって行うようにした
ことを特徴とする受信データ信号作成回路。1. In a received data signal generation circuit of a data communication modulation/demodulation device in which a demodulation circuit output and a carrier detection circuit output are ANDed by an AND circuit and output as a received data signal, the signal generation circuit is shorter than the carrier disconnection detection time of the carrier detection circuit. A received data signal characterized in that a second carrier detection circuit having a carrier disconnection detection time is provided, and the received data signal is created by performing a logical product including the output of the second carrier detection circuit. Create circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13408677A JPS5823023B2 (en) | 1977-11-10 | 1977-11-10 | Reception data signal generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13408677A JPS5823023B2 (en) | 1977-11-10 | 1977-11-10 | Reception data signal generation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5467711A JPS5467711A (en) | 1979-05-31 |
| JPS5823023B2 true JPS5823023B2 (en) | 1983-05-12 |
Family
ID=15120077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13408677A Expired JPS5823023B2 (en) | 1977-11-10 | 1977-11-10 | Reception data signal generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5823023B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6239942A (en) * | 1985-08-15 | 1987-02-20 | Toyo Commun Equip Co Ltd | Modulator and demodulator for data transmission |
-
1977
- 1977-11-10 JP JP13408677A patent/JPS5823023B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5467711A (en) | 1979-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6047531A (en) | Fail-safe circuit of multiple signal transmission system | |
| JPS5823023B2 (en) | Reception data signal generation circuit | |
| JPS6113251B2 (en) | ||
| US5701296A (en) | Reliable burst signal detecting apparatus | |
| JPS5840383B2 (en) | Line control method for data transmission equipment | |
| JP3221259B2 (en) | Bus type duplex transmission equipment | |
| KR100190602B1 (en) | Device of eliminating an unnecessary data in communication network | |
| JPS615654A (en) | Initial setting system of digital line terminator | |
| JPH0479630A (en) | Dual transmission systems | |
| JP2659070B2 (en) | IC card | |
| JPS6347294B2 (en) | ||
| JPH0470148A (en) | Power line carrier communication control equipment | |
| KR970005601B1 (en) | Method for recovering data in international maritime phase shift keying | |
| JPH05183605A (en) | Hardware control system for serial interface | |
| JPH04314226A (en) | Communication data protection circuit | |
| JPS6366090B2 (en) | ||
| JPS6386698A (en) | Remote supervisory and controlling equipment | |
| JPS6038952A (en) | Communication processing device | |
| JP2009088635A (en) | Communication device, transmitter, and receiver | |
| JPS62128634A (en) | Detecting circuit for abnormality of clock signal | |
| JPS58201450A (en) | Terminal controlling system | |
| JPH02270444A (en) | 2-wire full duplex/half-duplex switching device | |
| JPS61198823A (en) | System for detecting unconnection of input signal line | |
| JPH11112444A (en) | Loop back data collation method and its circuit | |
| JPH03239041A (en) | Alarm system |