JPS5821920A - Pulse amplifying circuit - Google Patents
Pulse amplifying circuitInfo
- Publication number
- JPS5821920A JPS5821920A JP12122681A JP12122681A JPS5821920A JP S5821920 A JPS5821920 A JP S5821920A JP 12122681 A JP12122681 A JP 12122681A JP 12122681 A JP12122681 A JP 12122681A JP S5821920 A JPS5821920 A JP S5821920A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- switching element
- terminal
- pulse
- pulse voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Landscapes
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はパルス増幅回路、特にプラズマディスプレイパ
ネル（以下ＦＤＰと略称する）や電場発光素子（以下Ｋ
Ｌと略称する）などの表示装置すなわち容量性真荷を駆
動するために用いられる高電圧パルス増幅回路に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to pulse amplification circuits, particularly plasma display panels (hereinafter referred to as FDP) and electroluminescent devices (hereinafter referred to as K).
The present invention relates to a high-voltage pulse amplification circuit used to drive a display device such as a capacitive load (abbreviated as L).
従来、上記のような表示装置を駆動するために用いられ
ていたパルス増幅回路は例えば第１図に示すようなもの
であった。すなわちこれは第１のスイッチング素子Ｑｕ
（以下アップスイッチング素子と呼ぶ）と１２のスイッ
チング素子Ｑｄ （以下ダウンスイッチング素子と呼ぶ
）を主とし、上記アップスイッチング素子Ｑｕｔａよび
リンギング防止用の第１のダイオードＤ１とで１種のカ
ソードフロワ↓
を形成しなる部分の出力端子２と、抵抗ＲａＪ６よびダ
ウンスイッチング素子Ｑｄからな９．１種のインバータ
を形成してなる部分の点Ｐとの間に導通路を与える第２
のダイオード込を接続してなる回路を構成し、該回路の
入力端子１には例えば波高値が５ｖ程度の入力パルス電
圧ｖ１を加え、出力端子２から例えば波高値が１００Ｖ
程度の出力パルス電圧Ｖｏを取秒出すものである。Conventionally, a pulse amplification circuit used to drive the above-mentioned display device is shown in FIG. 1, for example. That is, this is the first switching element Qu
(hereinafter referred to as up-switching elements) and 12 switching elements Qd (hereinafter referred to as down-switching elements), and together with the up-switching element Quta and the first diode D1 for ringing prevention, one type of cathode floor ↓ is formed. A second point providing a conductive path between the output terminal 2 of the formed part and the point P of the part formed of the 9.1 type inverter including the resistor RaJ6 and the down switching element Qd.
A circuit including a diode is connected, and an input pulse voltage v1 with a peak value of, for example, about 5 V is applied to the input terminal 1 of the circuit, and an input pulse voltage v1 with a peak value of, for example, about 100 V is applied from the output terminal 2.
It outputs an output pulse voltage Vo of about 10 seconds.
ところで、上記スイッチング素子中及びＱｄとしては、
一般にバイポーラトランジスタや第２図−）に示すよう
な絶縁ゲート形電界効果トランジス夕を用いた一路方式
が考えられている。ただし、この第２図（１）および１
１１図の１路において３は１００Ｖ程度の直流電源電圧
りを、また４は５Ｖ程度のゲートバイアス電圧ｖＧを、
それぞれ供給する端子であ怜、Ｃｏとして示したものは
前記表示素子の等価容量である。By the way, in the switching element and Qd,
In general, a one-way system using a bipolar transistor or an insulated gate field effect transistor as shown in Fig. 2-) has been considered. However, this figure 2 (1) and 1
In line 1 in Figure 11, 3 is the DC power supply voltage of about 100V, and 4 is the gate bias voltage vG of about 5V.
The terminals that are supplied, respectively, and are shown as Co, are equivalent capacitances of the display element.
Ｊ２図（８３のｉｉｔ路ｉ：＃イテＭＯ８Ｔ−Ｑａ Ｃ
ＩＪ、下！ ’１ンＭＯ８Ｔとも呼ぶ）がＭＯ３Ｔ−Ｑ
ｕ（以下アップＭＯ５Ｔとも呼ぶ）と同様に、例えば０
．５Ａ ９度の電流に耐えるような大電力型のものであ
れば、該ＭＯ８Ｔ−Ｑ、のソース・ドレイン関容量Ｃａ
は例えば１００〜２００ ＦＰ＠変の大きな値を有する
。仮に抵抗Ｒｅが例えばｌ０ＫＯの値を有するものであ
るならば、１（１−Ｃ４積で決まる時定数τは１〜２μ
ｗｅ程度となるために、第２図（転）中でＶｔとして示
した入カバ〜ス電圧が端子ｌに加わった場合に、ｔｒと
して示した時間にお叶る出力パルス電圧ＶＯの立上がり
すなわち曲線へは非常になまってしまってシャープなも
のでなくなってしまう。一方、立上がり（曲線へ）をシ
ャープにする目的で抵抗Ｒ６を小さな値に状態になり、
出力がグランドレベルになった時、電源Ｖ、から抵抗Ｒ
６を通し流れる無効電流が増え消費電力が増えるので得
策ではない。J2 diagram (83 iit path i: #iteMO8T-Qa C
IJ, bottom! '1-MO8T) is MO3T-Q
Similarly to u (hereinafter also referred to as up MO5T), for example, 0
．． If it is a high power type that can withstand a current of 5A 9 degrees, the source-drain capacitance Ca of the MO8T-Q is
has a large value of, for example, 100 to 200 FP. For example, if the resistance Re has a value of l0KO, the time constant τ determined by the product of 1 (1-C4) is 1 to 2 μ
When the input voltage shown as Vt in FIG. becomes very sloppy and no longer sharp. On the other hand, in order to sharpen the rise (to the curve), the resistor R6 is set to a small value,
When the output becomes ground level, the resistor R is connected from the power supply V.
This is not a good idea because the reactive current flowing through the circuit 6 will increase and the power consumption will increase.
また、第２ ’ＩＡ （ａ）に示したような回路は前記
したように表示装置に使用されるのであって、該回路の
すぐそばに、隣接して例えば１００ Ｖ程度のパルス高
さを発生する隣接回路があり、該回路において第２図（
ｃ）４こ示すような高い波高値のパルス電圧を発生して
いれば該回路で発生している上記パルス電圧は、静電誘
導によって第２図（ａ）の回路中の出力電圧Ｗｏｅこ、
第２図（ｂ）中でホとして示したような誘導パルス電圧
を生じさせ出力パルス電圧波形ＶＯは歪を生じてしまう
という欠点がある。In addition, the circuit shown in Section 2'IA (a) is used in a display device as described above, and a circuit that generates a pulse height of about 100 V, for example, is installed immediately adjacent to the circuit. There is an adjacent circuit in which the circuit shown in Fig. 2 (
c) 4 If a pulse voltage with a high peak value as shown in FIG.
There is a drawback that an induced pulse voltage as shown as E in FIG. 2(b) is generated, and the output pulse voltage waveform VO is distorted.
このＩＩＫ因は第２図（ｂ）中の点Ｐ１の出力電位が端
子３の電位ｖ８にまで立ち上がった後は、アップＭＯ３
Ｔ−Ｑｌｌのゲート電圧とソース電圧とが等しくなり、
該アップＭＯ５Ｔがオフ状態となって点Ｐ□の電位は漂
遊状態となってしまい、瞬間的な出力電流を供給できな
いことに基づいている。The reason for this IIK is that after the output potential at point P1 in FIG. 2(b) rises to the potential v8 at terminal 3, the
The gate voltage and source voltage of T-Qll become equal,
This is based on the fact that the up MO5T is turned off and the potential at point P□ becomes a stray state, making it impossible to supply an instantaneous output current.
本発明は上記の欠点に鑑みてなされたもので、前記アッ
プスイッチング素子の入力端子と接地間につながれたダ
ウンスイッチング素子を有するノ（ルス増幅鴎路におい
て、前記アップスイッチング素子の入力端子バイアス電
圧を該アップトランジスタの出力端子供給電圧よやも高
い電圧を有する別個の電源から供給するようにしたこと
を特徴とするパルス増幅回路を提供せんとするものであ
って、以下図画を用いて詳述する。The present invention has been made in view of the above-mentioned shortcomings, and includes a voltage amplification device having a down-switching element connected between the input terminal of the up-switching element and the ground. The present invention aims to provide a pulse amplifying circuit characterized in that the pulse amplifying circuit is supplied from a separate power source having a voltage higher than the voltage supplied to the output terminal of the up transistor, and will be described in detail below using drawings. .
第３１１は本発明に係るパルス増幅回路の一実施例を示
す一路であって、前記第２図と同等部位には開−符号を
付しである。Reference numeral 311 shows a circuit showing an embodiment of the pulse amplifying circuit according to the present invention, and the same parts as those in FIG. 2 are marked with an open symbol.
腋第３１１が前記第２ｇと太き（異なる所は、アップス
イッチング素子たるアップＭＯ８Ｔ−伽のゲートに抵抗
寵・を介してゲートバイアスＶ−を供給するのに、電源
端子３に印加されている電圧Ｖｓよ１）＆たとえばＬ５
僑程度高い別の電圧ｖ３から供給するようにした点であ
る。ただし、７は該電圧Ｖｍの供給端子である。The armpit No. 311 is thicker than the above-mentioned No. 2g (the difference is that the gate bias V- is applied to the power supply terminal 3 to supply the gate bias V- through the resistor to the gate of the up-switching element MO8T-. Voltage Vs 1) & for example L5
The point is that the voltage is supplied from another voltage v3 which is considerably higher. However, 7 is a supply terminal for the voltage Vm.
こうすればアップＭＯ３７−伽は常にオン状態にあるた
めに、出力端子２の電位すなわち点Ｐ、の電位は単連状
態になることはなく、該端子２の電位、 ゛したがって
出力パルス電圧ＶＯは、第３図（Ｑ中の］１として示し
た時間領域内では常にＶｓなる値を保つ。In this way, since the up MO37-- is always in the on state, the potential of the output terminal 2, that is, the potential of the point P, will not be in a single state, and the potential of the terminal 2, ゛Therefore, the output pulse voltage VO will be , in the time domain shown as 1 in FIG. 3 (in Q), the value Vs is always maintained.
そして上記のように、端子２の電位が漂遊状態にはない
ため壷こ、前記第２図（ｃ）に示したような高い波高値
のパルス電圧が第３図（ａ）の回路のすぐ側で発生して
も、ホとして示したような静電誘導による誘導パルス電
圧が発生することは抑制されてしまう。As mentioned above, since the potential at terminal 2 is not in a stray state, the pulse voltage with a high peak value as shown in FIG. 2(c) is applied immediately to the circuit in FIG. 3(a). Even if this occurs, the generation of the induced pulse voltage due to electrostatic induction as shown in E is suppressed.
さらに第３ＷＪ（ａ）の端子７に印加された電圧ＶＢは
例えば１５０ｖであり、このため・こ端子３に印加され
ている電圧■ｓよりも高くなっているため、前記したよ
うな抵抗Ｒａと容量Ｃｄとで決まる時定数で変化する出
力パルス電圧ｖＯのなだらかな立上がりすなわち曲線へ
はその立上がりをより急＃番こし、その結果数立上が快
特性は第３図（ｂ）中曇こ実線トで示したように急激な
ものとなるので、出力ノイルスミＪＥ Ｖｏの立上が１
）４Ｉ性のなまりは事実上非常に少なくなり、見かけ上
シャープなものとなるっすなわち以上に述べた本発明に
係るパルス増幅回路によれば、出力パルス電圧の立上が
りが事実上シャープになると共に、゛静電誘導による誘
導パルス電圧の発生を抑制する効果があるために、実用
上多大の効果が期待できる。Furthermore, the voltage VB applied to the terminal 7 of the third WJ (a) is, for example, 150V, and therefore is higher than the voltage s applied to the terminal 3, so the resistance Ra and The gradual rise of the output pulse voltage vO, which changes with a time constant determined by the capacitance Cd, is made more steep, and as a result, the rise is smoother. As shown in Figure 1, the rise of the output noise signal JE Vo is rapid.
) The 4I-like rounding is actually very reduced and the appearance is sharp. In other words, according to the pulse amplifying circuit according to the present invention described above, the rise of the output pulse voltage becomes sharp in fact, and ``Since it has the effect of suppressing the generation of induced pulse voltage due to electrostatic induction, it can be expected to have a great practical effect.
第１ＩＩは表示装置を駆動するために用いられていた従
来の回路、第２図（ａ）はスイッチング素子としてＨＯ
８Ｔを用いた回路例、そして第２図（ｂ）は該回路側の
入出力パルス波形を示す図であや、第２図（ｉは隣接−
路が生じるパルス波形、１３図（ａ）は本発明に係るパ
ルス増幅回路、１１３図（０はａＳＳを用いた場合の入
力パルス電圧Ｖｔを出力パルス電圧ＶＯと共に示したー
である。
ｌ：入力端子、２：出力端子、３，４．７ ：電圧供給
端子、ｃｏ：表示素子の容量性真荷、Ｃａ：ダウンスイ
ッチング素子の出力容量、Ｄ、、 Ｄ、 ｊダイオード
、ＱＩＩニアツブスイッチング素子、Ｑｄ：ダウンスイ
ッチング素子。
第１図 第２図（（１）
第 ２図（ｂ）
第２図＜ｃ）
第３図
（Ｑ） （ｂ）1II is a conventional circuit used to drive a display device, and FIG. 2(a) shows an HO as a switching element.
An example of a circuit using 8T, and FIG. 2(b) is a diagram showing the input/output pulse waveforms on the circuit side.
Figure 13 (a) shows the pulse waveform in which the pulse waveform occurs, and Figure 113 (a) shows the pulse amplification circuit according to the present invention. Terminal, 2: Output terminal, 3, 4.7: Voltage supply terminal, co: Capacitive true load of display element, Ca: Output capacitance of down switching element, D, D, j diode, QII near tube switching element, Qd: Down switching element. Fig. 1 Fig. 2 ((1) Fig. 2 (b) Fig. 2<c) Fig. 3 (Q) (b)
Claims (1)
素子と該アップスイッチング素子の出力端子と接地間に
゛つながれたダイオードおよび上記出力端子とアップス
イッチング素子の入力端子との間に導通路を与えるダイ
オードを有すると共に前記アップスイッチング素子の入
力端子と接地間につながれたダウンスイッチング素子を
有するパルス増幅回路に動いて、前記アップスイッチン
グ素子の入力端子に接続したバイアス用の抵抗を上記の
電源よりも高い電圧を有する別個の電源に接続したこと
を特徴とするパルス増幅回路。An up-switching element connected between a power supply and an output terminal, a diode connected between the output terminal of the up-switching element and ground, and a diode providing a conductive path between the output terminal and the input terminal of the up-switching element. and a down-switching element connected between the input terminal of the up-switching element and ground, the bias resistor connected to the input terminal of the up-switching element is connected to a voltage higher than the power source. A pulse amplification circuit, characterized in that the pulse amplification circuit is connected to a separate power supply having:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12122681A JPS5821920A (en) | 1981-07-31 | 1981-07-31 | Pulse amplifying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12122681A JPS5821920A (en) | 1981-07-31 | 1981-07-31 | Pulse amplifying circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5821920A true JPS5821920A (en) | 1983-02-09 |
Family
ID=14806016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12122681A Pending JPS5821920A (en) | 1981-07-31 | 1981-07-31 | Pulse amplifying circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5821920A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60208119A (en) * | 1984-03-30 | 1985-10-19 | Hitachi Ltd | Semiconductor switch |
| JPS6399616A (en) * | 1986-03-24 | 1988-04-30 | Matsushita Electric Works Ltd | Solid-state relay and its manufacture |
| JPS6484917A (en) * | 1988-08-08 | 1989-03-30 | Hitachi Ltd | Semiconductor integrated circuit |
-
1981
- 1981-07-31 JP JP12122681A patent/JPS5821920A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60208119A (en) * | 1984-03-30 | 1985-10-19 | Hitachi Ltd | Semiconductor switch |
| JPH0414806B2 (en) * | 1984-03-30 | 1992-03-16 | Hitachi Seisakusho Kk | |
| JPS6399616A (en) * | 1986-03-24 | 1988-04-30 | Matsushita Electric Works Ltd | Solid-state relay and its manufacture |
| JPH0478210B2 (en) * | 1986-03-24 | 1992-12-10 | Matsushita Electric Works Ltd | |
| JPS6484917A (en) * | 1988-08-08 | 1989-03-30 | Hitachi Ltd | Semiconductor integrated circuit |
| JPH0638578B2 (en) * | 1988-08-08 | 1994-05-18 | 株式会社日立製作所 | Semiconductor integrated circuit device |
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