JPS58204594A - Method of producing printed circuit board - Google Patents
Method of producing printed circuit boardInfo
- Publication number
- JPS58204594A JPS58204594A JP8749282A JP8749282A JPS58204594A JP S58204594 A JPS58204594 A JP S58204594A JP 8749282 A JP8749282 A JP 8749282A JP 8749282 A JP8749282 A JP 8749282A JP S58204594 A JPS58204594 A JP S58204594A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- solder resist
- circuit board
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明はプリント配線板の製造方法に関し、特に絶縁基
板上に形成さ几た導体贋金選択的に覆ってツルグー・レ
ジスト層が被覆されるプリント配線板の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and in particular to a method for manufacturing a printed wiring board, in particular a printed wiring board in which a printed circuit board is selectively covered with a conductive resist layer formed on an insulating substrate. The present invention relates to a method for manufacturing a wiring board.
（２） 技術の背景
電子計算機等の電子機器にあっては、半導体集積回路素
子等の高集積化に伴い、よシ小梨化、高性能化が図らｎ
つつある。(2) Background of the technology Electronic devices such as computers are becoming smaller and more sophisticated as semiconductor integrated circuit elements become more highly integrated.
It's coming.
かかる電子機器にあっては、前記半導体集積回路装置等
の電子部品ｆＣ実装し、所望の電子回路全構成する手段
として、プリント配線板が用いられている。半導体集積
回路素子の高集積化に伴い、プリント配線板における実
装密度の同上が要求さｎている。In such electronic equipment, a printed wiring board is used as a means for mounting electronic components fC such as the semiconductor integrated circuit device and configuring all desired electronic circuits. As semiconductor integrated circuit elements become more highly integrated, higher packaging density on printed wiring boards is required.
かかるプリント配線板の製造においては、絶縁基板表面
に形成された導電層（配線層、部品実装用ランド）上及
びその相互間に、ソルダー・レジストと称される樹脂皮
膜が選択的に形成、配置さｎる。In manufacturing such printed wiring boards, a resin film called solder resist is selectively formed and arranged on the conductive layer (wiring layer, component mounting land) formed on the surface of the insulating substrate and between them. Sanru.
かかるソルダー・レジストは、前記部品実装用ランドへ
部品の端子を挿入し、これを半田浴へ接触させて、部品
の端子を部品実装用ランドへ半田付けによシ固着する際
に、かかる半田が不所望の領域において近接する導電層
間に橋絡状に付着して短絡等を生ずることを防止するた
めに用いられるものである。Such a solder resist is used when the terminal of a component is inserted into the land for component mounting, brought into contact with a solder bath, and fixed by soldering to the land for component mounting. This is used to prevent adhesion between adjacent conductive layers in an undesired region in the form of a bridge, resulting in a short circuit or the like.
かかるソルダー・レジストとしてｕ、ｉｉ、プリント配
線基板上に、いわゆるスクリーン印刷法によって所望パ
ターンに塗布、形成さｎるものと、感光性のフィルム状
金有しプリント配線基板上に貼り付けられ所望パターン
の露光、現慮処理がなされて形成されるフォト・ソルダ
ー・レジスト層が用いらｎでいる。Such solder resists include those that are coated and formed into a desired pattern on a printed wiring board by the so-called screen printing method, and those that are pasted onto a printed wiring board that has a photosensitive film-like metal and have a desired pattern. A photo solder resist layer formed by exposure and practical processing is used.
（３）従来仮術と問題点
しかしながら、前述の如く高密度の実装が要求さｎるプ
リント配線板にあっては、かかるソルダー・レジストの
パターンにも当然高精度が要求さｎる。従ってソルダー
・レジストトシてハ、フォト・ツルグー・レジストが用
いられる１頃向にあるＯ
ところがかかるフォト・ソルダー・レジス）Ｕ予めフィ
ルム状に形成して因るために表面子滑性汲 、
が高く、光況もあり、このため、かかる７ｆト・ソルダ
ー・レジスト層が表面に形成されたプリント配線板に部
品端子金挿入し半田浴に接触させた場合に、半田ボール
が発生し易いことが判明した。(3) Conventional techniques and problems However, as mentioned above, printed wiring boards that require high-density packaging naturally require high precision in the solder resist pattern. Therefore, since the photo solder resist is formed in advance into a film, the surface lubricity is high. Due to the light conditions, it was found that solder balls were likely to occur when a component terminal metal was inserted into a printed wiring board with such a 7ft solder resist layer formed on the surface and brought into contact with a solder bath. did.
い
かかる半田ボールはフォト−ツルグー・レジスト・、ｊ
、′
上において近接する導体層間あるいは部品端子間に橋絡
状に接触し、不要な短絡音生ずる一因となる。The solder balls that appear are photo-Tsurugu Resist.
, ', there is a bridge-like contact between adjacent conductor layers or between component terminals, which contributes to the generation of unnecessary short-circuit noise.
すなわち、当該プリント配線板の製造歩留り、信頼性全
低下させる一因となる。In other words, this becomes a factor that completely reduces the manufacturing yield and reliability of the printed wiring board.
（４）発明の目的
本発明はプリント配線板の製造において、前記フォト・
ソルダー・レジストヲ用いても半田ボール金主ずること
ない裏道方法を提供しようとするものである。(4) Purpose of the Invention The present invention provides a method for manufacturing printed wiring boards.
The purpose is to provide a back-door method that does not involve the use of solder balls even when solder resist is used.
（５）発明の構成
このため、本発明によれば、絶縁基板上に形成された導
電層を選択的に覆うノルグー・レジスト層の表面を、粗
面化する工程を有するプリント配線板の裏道方法が提供
される。(5) Structure of the Invention Therefore, according to the present invention, a method for backtracking a printed wiring board includes the step of roughening the surface of a Norgu resist layer that selectively covers a conductive layer formed on an insulating substrate. is provided.
以下本発明を実施側音もって詳細に説明する。Hereinafter, the present invention will be explained in detail with reference to its implementation.
（６）発明の実施例
本発明に二ｎば、次の方法により、プリント配線基板上
へのフォト・ソルダー・レジスト層の形成が行わｎる〇
□
すなわち、まず所望″９導電層が形成さｎｆｃプリント
配線基板上へのフォト・ソルダー・レジストフィルム（
厚さ′２Ｑ〔μｍ〕’ｌの貼り付けが行なわｎる。(6) Embodiments of the Invention According to the present invention, a photo solder resist layer is formed on a printed wiring board by the following method. Namely, a desired conductive layer is first formed. Photo solder resist film on NFC printed wiring board (
Pasting with a thickness of '2Q [μm]'l is performed.
次いで、前記フォト・ソルダー・レジストフィルムへ所
望パターンの露光処理がなされる。Next, the photo solder resist film is exposed to light in a desired pattern.
次いで前記フォト・ソルダー・レジストフィルムの現癲
処理が行わル、その不要部分が除去さｒる。かかる現像
処理により、部品実装用ランド等必要な導電層が露出さ
れる。Next, the photo solder resist film is subjected to a developing process, and unnecessary portions thereof are removed. Through this development process, necessary conductive layers such as component mounting lands are exposed.
次いで前記プリント配線基板上に残さまたフォト・ソル
ダー・レジスト層の表面を７００番程鹿の砥粒及び／又
はブフシによって研削し、該フォト・ソルダー・レジス
ト層の表面金柑面化する。Next, the surface of the photo solder resist layer left on the printed wiring board is ground using a No. 700 deer abrasive and/or a brush to give the surface of the photo solder resist layer a kumquat surface.
以上の処理（よって、プリンｂ配Ｈｓ板よに残さｎるフ
ォト・ソルダー・レジスト層はその表面が粗面化さｎる
。As a result of the above processing (therefore, the surface of the photo solder resist layer left on the printed wiring board becomes rough).
この結果、かかるプリント配線板の部品実装用ランドに
部品端子金挿入して後、かかるプリント配線板を半田浴
に接触しても、半田ボールは発生しない。As a result, even if the printed wiring board is brought into contact with the solder bath after the component terminal metal is inserted into the component mounting land of the printed wiring board, no solder balls are generated.
（７）発明の効果
以上のように、本発明によルば、導電層上音１ってソル
ダー・レジスト層が配設さルるプリント配組板の製造に
おいて、ソルダー・レジスト層の表面を粗面化すること
により、当該プリント配線板の半田浴への接触の際に半
田ボール金主ずることがない。(7) Effects of the Invention As described above, according to the present invention, in the production of printed wiring boards on which a conductive layer 1 is provided with a solder resist layer, the surface of the solder resist layer is By roughening the surface, the solder balls will not be exposed when the printed wiring board contacts the solder bath.
従って当該プリント配線板の製造歩留り及び信頼性全署
しく高めることができる。Therefore, the manufacturing yield and reliability of the printed wiring board can be improved completely.
Claims (1)
ー・レジスト層の表面を、粗面化する工程を有すること
ｔ−特徴とするプリント配線板の製造方法。A method for manufacturing a printed wiring board, comprising the step of roughening the surface of a solder resist layer that selectively covers a conductive layer formed on an insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8749282A JPS58204594A (en) | 1982-05-24 | 1982-05-24 | Method of producing printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8749282A JPS58204594A (en) | 1982-05-24 | 1982-05-24 | Method of producing printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58204594A true JPS58204594A (en) | 1983-11-29 |
Family
ID=13916449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8749282A Pending JPS58204594A (en) | 1982-05-24 | 1982-05-24 | Method of producing printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58204594A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56127633A (en) * | 1980-01-30 | 1981-10-06 | Siemens Ag | Matte finish of high brilliant resin surface of conductor plate |
| JPS5758389A (en) * | 1980-09-24 | 1982-04-08 | Hitachi Chemical Co Ltd | Method of producing printed circuit board |
-
1982
- 1982-05-24 JP JP8749282A patent/JPS58204594A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56127633A (en) * | 1980-01-30 | 1981-10-06 | Siemens Ag | Matte finish of high brilliant resin surface of conductor plate |
| JPS5758389A (en) * | 1980-09-24 | 1982-04-08 | Hitachi Chemical Co Ltd | Method of producing printed circuit board |
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