JPS58164231A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58164231A JPS58164231A JP4624482A JP4624482A JPS58164231A JP S58164231 A JPS58164231 A JP S58164231A JP 4624482 A JP4624482 A JP 4624482A JP 4624482 A JP4624482 A JP 4624482A JP S58164231 A JPS58164231 A JP S58164231A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor substrate
- compensating plate
- acid
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分計〕
この発明は半導体装置の製造方法に係り、１ＶＩＫ会金
による方法及び圧接による方法によって電極を取り出し
ている半導体装置の製造方法において。DETAILED DESCRIPTION OF THE INVENTION [Technical summary to which the invention pertains] The present invention relates to a method for manufacturing a semiconductor device, and a method for manufacturing a semiconductor device in which electrodes are taken out by a method using 1VIK metal and a method using pressure welding.
電極圧接時の面内圧力分布の不均一を緩和する半導体装
、１の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device 1 that alleviates unevenness in in-plane pressure distribution during electrode pressure contact.
一般に、半導体基体と金属板との合金によりアノード電
極を形成し、半導体基体金属と会＠板の圧接によやカソ
ード電極を取や出す方法を用いている大電力用のサイリ
スタやゲートターンオフサイリスタは、加圧圧接時にカ
ノード電１ｍにおいて、≠導体基体金属と金属板間の平
面方向の圧力分布が不均一に′＆る。この王な原因は、
アノード電極として使用する温度補償板と半導体４体と
の熱膨張係数が這うため、合金工程時の加熱、冷却に伴
なうバイメタル効果によって素子全体が湾曲する九めで
ある。このと愈のカソード電嘱圧接の断面ｌ媚＋１ｌ−
ｓ１１ｉｉに示す。ｑυはシリコン等からなる半導体基
体、ｑ２は半導体基体のカソード電極、 （１３はカソ
ード電極ポスト、ｔ１４はａｍ補償板である。In general, high-power thyristors and gate turn-off thyristors use a method in which the anode electrode is formed from an alloy of a semiconductor substrate and a metal plate, and the cathode electrode is removed after pressure contact between the semiconductor substrate metal and the plate. During pressure welding, the pressure distribution in the plane direction between the conductor base metal and the metal plate becomes non-uniform at 1 m of the cathode electrode. This royal cause is
Since the thermal expansion coefficients of the temperature compensating plate used as an anode electrode and the four semiconductor bodies are different, the entire element is curved due to the bimetallic effect accompanying heating and cooling during the alloying process. The cross section of this and Yu's cathode voltage pressure welding is +1l-
It is shown in s11ii. qυ is a semiconductor substrate made of silicon or the like, q2 is a cathode electrode of the semiconductor substrate, (13 is a cathode electrode post, and t14 is an am compensation plate.
従来は、半導体基体を構成するシリコンの熱膨張係数に
近い熱膨張係数をもつ、タングステンやモリブデンなど
の金属を温度補償板に使用することに上り上記間ＩＩＫ
対する改良を麿してきた。−列として、第２図にシリコ
ン基板とタングステン板による従来の合金工程の断面図
を示す、又、この前後の工程は、本発明に直接関係がな
いので省略する。第２図（３１）は合金工椙前であり、
０υはシリコン基体、α４はタングステン等からなるａ
ｔ補償板％ａ勾はアルミニウム箔である。この系のア四
イは、シリコン基板とアルミニウム箔、アルミニウム箔
とタングステン板の２ａｌ類の合金が行なわれる。前者
の共晶＠度は７１０℃、後者の共晶＠賓は６９０℃なの
で７１０℃以上に加熱すればこれらを一体化することが
できる。ｔ４２図（ｂ）は合金工程後である。タングス
テンは、シリコンに比べてａｍ張係数が６倍程度あり、
７１０℃で共晶し九後、冷却すると、バイメタル効果に
よって合金工程後は第２図（ｂ）のように湾曲し九１ｆ
Ｎｃｆｋる。Ｏｅは合金層で、αηは湾曲によって生じ
たシリコン基板の中心と周辺部の反抄長である。−例□
として、シリコン基板の厚さを６００Ａｍ１タングステ
ン板の厚さ３關、各々の直径を６ｃｍとし九時の反抄長
は約１００μｍ程度であり、カンード電極圧接時の平面
方向の圧力不均一は必至である。Conventionally, metals such as tungsten and molybdenum, which have a coefficient of thermal expansion close to that of silicon constituting the semiconductor substrate, have been used for the temperature compensating plate.
We have made progress in improving this. FIG. 2 shows a cross-sectional view of a conventional alloying process using a silicon substrate and a tungsten plate, and the steps before and after this are not directly related to the present invention and will therefore be omitted. Figure 2 (31) is in front of Alloy Koshu;
0υ is a silicon base, α4 is a made of tungsten, etc.
The compensator plate %a is made of aluminum foil. In this system, 2al alloys of a silicon substrate and an aluminum foil, and an aluminum foil and a tungsten plate are used. The former's eutectic temperature is 710°C, and the latter's eutectic temperature is 690°C, so they can be integrated by heating to 710°C or higher. Figure t42 (b) is after the alloying process. Tungsten has an am tensile coefficient of about 6 times that of silicon.
After eutectic crystallization at 710°C, when cooled, the alloy process becomes curved as shown in Figure 2(b) due to the bimetallic effect.
Ncfkru. Oe is the alloy layer, and αη is the length of retraction at the center and periphery of the silicon substrate caused by the curvature. −Example□
Assuming that the thickness of the silicon substrate is 600 Am, the thickness of each tungsten plate is 3 cm, and the diameter of each is 6 cm, the length of the 9 o'clock retraction is about 100 μm, and pressure non-uniformity in the plane direction is inevitable when canned electrodes are pressed. be.
本発明はｂ記欠点についてなされたもので、特に合会工
！＠ｆ！ＩｊＫ半導体基体表面を球面状に加工すること
てよ抄、合金工程後の半導体基体表面をほぼ平らにし、
カノード電橿圧接時の平面方向の圧力不均一を緩和する
半導体Ｉｓ萱の製造方法を提供するととくある。The present invention has been made to address the drawbacks listed in b. @f! To process the IjK semiconductor substrate surface into a spherical shape, the semiconductor substrate surface after the alloying process is made almost flat,
It is an object of the present invention to provide a method for manufacturing a semiconductor IS-port which alleviates pressure non-uniformity in the plane direction during pressure welding of a cathode electrode.
第３図に本発明の製造方法による合金工程の断面・Ａを
示す、第３図（噂は合会工福前であり、１３０は本発明
（より加工し九半導体基体、ａ！９はアルミニウム箔、
０４は温度補償板で、第３図（ｂ）は合金工程後で、１
・は合金属である０次に第３１！ＩＩ（ａ）の半導体基
体らυの表面を球面状〈加工する加工法及び加工量を以
下に示す、半導体基体Ｃ（υの表面を球面状に加工する
方法としては、機械的に行う研摩又は薬品によるエツチ
ングなどがあるが、機械的に行う研ｌｌは、半導体基板
０１ｍ面に欠陥を作秒ヤすいため、薬品によるエツチン
グが望ましい、以下、薬品による加工法を第４１１に−
ｔ−りて述べる。まず、 ′第４図１ａ）のように半
導体基体１３０表面のアノード側を耐彎性の物質からな
る保−膜（４８ｍ） 、丙えはワックスやテープなどで
覆い、エツチング液から保護する０次に弗酸と硝酸の混
合液にてエツチングする。なお弗酸と硝酸の？ｊ＆比及
びエラチン（グ時間は後述する０次に、第４図（ｂ）の
ように半導体基体ｃ３Ｉのカソード側に上記と同じよう
に保護ＩＩ （４ｍ）を形成し、弗酸と硝酸の混合液如
てエツチングする。４４図（ｃ）は半導体基体Ｇ１）の
加工後の断面図であり、−は半導体基体の中心と周辺の
加工量の差である。第５図にエツチング液の弗酸と硝酸
の混合比を賓えた時の半導体躯体の中心（ａ）と周辺（
ｂ）のエツチング速度を示す、なおこの図はエツチング
液の温度が２２〜２３℃におけるものである。−例とし
て、半導体基体Ｇｏの中心と周辺の加工量の差を１００
μｆｎ Ｋする場合のエツチング液の１合比焚びエツチ
ング時間を以下に述べる。第５図より半導体基体の中心
と周辺の加工量の差を１００μｍＫする場合、弗酸と硝
酸の混合比が１対０．３の液により半導体基体のカソー
ド側を２０分関上配方法により加工し、次に弗酸と硝酸
の混合比が１対３の液により半導体基体のアノード側を
２０分間上１方法により加工することで達成される。直
径６１のシリコン基帷と直＠＠ＣＳのタングステン板を
使って各々の厚みを変えた場合、半導体基体の中心と一
辺の加工量の差の蝋適値は表−ＩＫ示すとお秒である。Figure 3 shows the cross section A of the alloy process according to the manufacturing method of the present invention. foil,
04 is a temperature compensating plate, and Figure 3 (b) shows 1 after the alloying process.
・is the 0th order 31st which is an alloy metal! The surface of the semiconductor substrate C (υ) of II (a) is processed into a spherical shape (the processing method and amount of processing are shown below). Although there are etching methods using chemicals, mechanical etching is preferable because it removes defects on the surface of the semiconductor substrate 01m.
Let's talk about it. First, as shown in Figure 4 1a), the anode side of the surface of the semiconductor substrate 130 is covered with a protective film (48 m) made of a curvature-resistant material, and then with wax or tape to protect it from the etching solution. Etch using a mixture of hydrofluoric acid and nitric acid. What about hydrofluoric acid and nitric acid? Next, as shown in FIG. 4(b), protection II (4m) was formed on the cathode side of the semiconductor substrate c3I in the same manner as above, and a mixture of hydrofluoric acid and nitric acid was added. 44(c) is a cross-sectional view of the semiconductor substrate G1) after processing, and - is the difference in the amount of processing between the center and the periphery of the semiconductor substrate. Figure 5 shows the center (a) and periphery (a) of the semiconductor body when the mixing ratio of hydrofluoric acid and nitric acid in the etching solution is changed.
This figure showing the etching rate in b) is obtained when the temperature of the etching solution is 22 to 23°C. - As an example, the difference in processing amount between the center and the periphery of the semiconductor substrate Go is 100
The etching time and firing ratio of the etching solution in the case of μfnK is described below. From Fig. 5, when the difference in processing amount between the center and the periphery of the semiconductor substrate is 100 μmK, the cathode side of the semiconductor substrate is processed using a liquid with a mixture ratio of hydrofluoric acid and nitric acid of 1:0.3 for 20 minutes using the above method. Then, the anode side of the semiconductor substrate is processed by the above method for 20 minutes using a solution containing hydrofluoric acid and nitric acid in a mixing ratio of 1:3. When using a silicon substrate with a diameter of 61 mm and a tungsten plate with a straight @@CS, and changing the thickness of each, the appropriate value for the difference in processing amount between the center and one side of the semiconductor substrate is 1/2 second as shown in Table IK.
表−１
〔発明の効果〕
次に本発明の効果を説明する０本発明の製造方法１ｄ、
合金工程によ抄半導体基体ｓ、ｍが湾曲する量をちらか
しめ半導体基体ｓ１を球面状に加工することが特徴であ
る６合金工程などのように２種類の物質を頓着させ九場
合、一方の物質の厚みをｆｉ場に厚くしなければ、温度
が変化した時そのバイメタル効ＮｋＫよって一方に湾曲
する。一方、本発明による製造方法によれば、半導体薔
体又唸温度補償板の一方又は両方を薄くしても合会工鴇
後の半導体表面をほぼ平らＫでき、電極圧接時（平面方
向の圧力分布の不均一を緩和することを可能にする。Table 1 [Effects of the Invention] Next, the effects of the present invention will be explained.0 Manufacturing method of the present invention 1d,
The alloying process is characterized by reducing the amount of curvature of the semiconductor substrates s and m and processing the semiconductor substrate s1 into a spherical shape.6 In the case where two types of substances are brought together as in the alloying process, one of the If the thickness of the material is not made thicker than the fi field, it will curve to one side due to the bimetallic effect NkK when the temperature changes. On the other hand, according to the manufacturing method of the present invention, even if one or both of the semiconductor body and the temperature compensation plate are thinned, the semiconductor surface after bonding can be made almost flat, and when electrode pressure is welded (pressure in the plane direction This makes it possible to alleviate uneven distribution.
本発明の実権例によれば、直径６１で厚さが１０００μ
ｍのシリコン基体と直径６ｃｍで厚さが３關のタングス
テン板において、シリコン基体のアノード側を耐酸性の
テープで保護し、弗酸と鋼管の混合比が１対０．３のエ
ツチング液で２０分間エツチングする。さらにシリコン
基体のアノード側を露出させ、カノード側を耐酸性のテ
ープで保護し弗酸と硝酸の混合比が１対７のエツチング
液で１０分間エツチングする。このシリコン基体と上記
のタン・ゲステン板により合金した賭果、シリコン基体
表面の凹凸は±５μｍ以内に収まった。第６図に従来方
法で合金した時の平面方向の圧力分布と本１！廁例で合
金した時の平面方向の圧力分布を示す。なお両者とも厚
さ、直径、電極王接叶同じである。＠６図（ａ）Ｆ１従
来方法によ）合金した時の平面方向の圧力分有を示し、
第６１１（ｂ）は本実権９１によ知合会した時の平面方
向の圧力分布を示す。According to the practical example of the present invention, the diameter is 61 and the thickness is 1000 μm.
A tungsten plate with a diameter of 6 cm and a thickness of 3 mm is used, the anode side of the silicon substrate is protected with an acid-resistant tape, and etched with an etching solution with a mixing ratio of hydrofluoric acid and steel pipe of 1:0.3. Etch for a minute. Further, the anode side of the silicon substrate is exposed, the cathode side is protected with acid-resistant tape, and etched for 10 minutes with an etching solution containing hydrofluoric acid and nitric acid in a mixing ratio of 1:7. As a result of alloying this silicon substrate with the above-mentioned Tan-Gesten plate, the unevenness on the surface of the silicon substrate was within ±5 μm. Figure 6 shows the pressure distribution in the plane direction when alloyed using the conventional method and Book 1! This shows the pressure distribution in the plane direction when alloyed in the example. Note that both have the same thickness, diameter, and electrode crown. @Figure 6 (a) F1 Shows the pressure distribution in the plane direction when alloyed (by conventional method),
No. 611(b) shows the pressure distribution in the plane direction when the actual power 91 is met.
第６＠よ抄、従来方法で合金し友時の平面方向の圧力分
布は半導体基体の局迎に比べて中心付近が約６倍ｍｍで
ある０本夷論例によれば、半導体基体の平１方向の圧力
分布は１周辺に比べて中心が約２倍ｍｍであう九。No. 6 @yosho: According to the zero theory example, the pressure distribution in the plane direction when alloyed using the conventional method is approximately 6 times mm near the center compared to the local pressure distribution of the semiconductor substrate. The pressure distribution in one direction is about twice as wide at the center as it is at the periphery.
上配夷１ｓｆｌｌではシリコン基体とタングステン板に
おいて行なったが、シリコンの他、ガリウムリンなど化
合物半導体と、モリブデン板等の半導体基体と熱膨張係
数が比較的同じものにても同様に適用できるのは轟然で
ある。In the above 1sfll, the study was carried out on a silicon substrate and a tungsten plate, but it can also be applied to compounds with relatively the same coefficient of thermal expansion as semiconductor substrates such as silicon, compound semiconductors such as gallium phosphide, and semiconductor substrates such as molybdenum plates. It's roaring.
第１Ｉは、従来Ｏ方法によ抄合金した半導体装置に電極
を８ＥＩＩＬ、え断Ｗ図、第２図は従来の合会工椙と合
ｆＩ！優の断ｇ＠、第３１Ｅｌｔｉ本発明による合金工
種と合金後のｌｌｌ’ｒ−閏、第４閏は本発明による半
導体基体の加工方法の断面図、第５図は弗酸と硝酸の混
合比を変え九時の半導体基体のエツチング速度を示す図
、第６図は、従来方法によ抄会会した物と本実権例で合
金した物との平面方向の圧力分布を示す図である。
３１：半導体基体、１４：ａ度補償板、１５：アルＺニ
ウム箔。
４８ｇ＝４８ｂ ：保穫膜。
ｌ
第１図
第２図
第３図
第６図
辺 ゝ 巧Fig. 1I shows an electrode formed on a semiconductor device manufactured by the conventional method O, and Fig. 2 shows a conventional method of forming an electrode and an electrode. Excellent cutting g@, 31st Elti Alloy processing type according to the present invention and lll'r after alloying, the fourth leap is a cross-sectional view of the processing method of a semiconductor substrate according to the present invention, and Fig. 5 is the mixing ratio of hydrofluoric acid and nitric acid. FIG. 6 is a diagram showing the etching rate of the semiconductor substrate at 9 times when the wafer is changed, and FIG. 6 is a diagram showing the pressure distribution in the plane direction of the material assembled by the conventional method and the material alloyed in this practical example. 31: Semiconductor substrate, 14: A-degree compensator, 15: Al-Z foil. 48g=48b: Preservative film. l Figure 1 Figure 2 Figure 3 Figure 6 side ゝ Takumi
Claims (1)
基体と、該半導体基体の少なくとも一方側に設けられた
温度補償板とから成る半導体装置において、前記半導体
基体の少なくとも一方の主面をあらかじめ球面状に加工
した後ａｔ補償板と合金させて、半導体装置表面をほぼ
平らにすることを特徴とする半導体装置の製造方法。In a semiconductor device comprising a semiconductor substrate having two main surfaces and one or more PN junctions, and a temperature compensating plate provided on at least one side of the semiconductor substrate, at least one main surface of the semiconductor substrate is A method for manufacturing a semiconductor device, which comprises processing the semiconductor device into a spherical shape in advance and then alloying it with an AT compensator to make the surface of the semiconductor device substantially flat.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4624482A JPS58164231A (en) | 1982-03-25 | 1982-03-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4624482A JPS58164231A (en) | 1982-03-25 | 1982-03-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58164231A true JPS58164231A (en) | 1983-09-29 |
Family
ID=12741726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4624482A Pending JPS58164231A (en) | 1982-03-25 | 1982-03-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58164231A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60189937A (en) * | 1984-03-12 | 1985-09-27 | Fujitsu Ltd | Applicator of resist |
| US7199448B2 (en) | 2001-02-14 | 2007-04-03 | Infineon Technologies Ag | Integrated circuit configuration comprising a sheet-like substrate |
| CN103871837A (en) * | 2012-12-18 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Method for improving warping degree of wafer |
-
1982
- 1982-03-25 JP JP4624482A patent/JPS58164231A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60189937A (en) * | 1984-03-12 | 1985-09-27 | Fujitsu Ltd | Applicator of resist |
| US7199448B2 (en) | 2001-02-14 | 2007-04-03 | Infineon Technologies Ag | Integrated circuit configuration comprising a sheet-like substrate |
| CN103871837A (en) * | 2012-12-18 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Method for improving warping degree of wafer |
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