JPS59939A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59939A
JPS59939A JP10977082A JP10977082A JPS59939A JP S59939 A JPS59939 A JP S59939A JP 10977082 A JP10977082 A JP 10977082A JP 10977082 A JP10977082 A JP 10977082A JP S59939 A JPS59939 A JP S59939A
Authority
JP
Japan
Prior art keywords
layer
active layer
silicon
film
internal stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10977082A
Other languages
Japanese (ja)
Inventor
Masayoshi Sasaki
佐々木　正義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP10977082A priority Critical patent/JPS59939A/en
Publication of JPS59939A publication Critical patent/JPS59939A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To prevent a crack from occurring at a semiconductor device by forming a semiconductor element active layer via a thin semiconductor film and an insulating film on an insulating substrate. CONSTITUTION:When polycrystalline Si is melted and recrystallized to obtain an Si element active layer 34, a quartz substrate 31 itself does not, since a polycrystalline Si buffer layer 32 is presented under the layer 34, rise its temperature to the melting point of the Si. Accordingly, even this can alleviate the production of an internal stress due to the difference of thermal expansions, and, since a buffer layer exists, the internal stress due to the difference of the thermal expansions is dispersed to the layer 32 and an Si oxidized film 33, or the film 33 and the layer 34, and the internal stress in the active layer can be remarkably decreased as compared with the case that no buffer and Si oxidized film are presented.

Description

【発明の詳細な説明】 この発明は絶縁物基板上に半導体素子能動層を有する半
導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a semiconductor element active layer on an insulating substrate.

従来、石英基板上にシリコン素子能動層を形成する方法
として、グ′）７オエビタキシイ技術が知られている。Conventionally, as a method for forming a silicon element active layer on a quartz substrate, the 7-layer taxi technique is known.

これは、第１図に示すように、石英基板１にレリーフを
形成し、このレリーフ形状を反映したシリコン結晶成長
を行なってシリコン層２を形成し、半導体能動層を得る
ものである。In this method, as shown in FIG. 1, a relief is formed on a quartz substrate 1, and a silicon layer 2 is formed by growing a silicon crystal reflecting the relief shape to obtain a semiconductor active layer.

しかし、この方法では、結晶形成方法として、多結晶シ
リコンをレーザなどで溶融し、再結晶させる方法を用い
ているために１石英基板１１とシリコン層１２との熱膨
張係数の相違によ）、第２図に示すように、シリコン層
１２に大きな内部応力１４が発生し、多くの場合に、シ
リコン層１２にクラック１３が発生するという問題があ
った。However, this method uses a method of melting polycrystalline silicon with a laser or the like and recrystallizing it as a crystal formation method. As shown in FIG. 2, there is a problem in that a large internal stress 14 is generated in the silicon layer 12, and cracks 13 are generated in the silicon layer 12 in many cases.

すなわち、石英の熱膨張係数は０．０５５　ｘ　１０　
／（１ｅｇであシ、シリコンの熱膨張係数は０．４２×
１０／ｄｅｇであるので、シリコンの溶融温度である１
４２０℃から常温まで変化すると、シリコン層に引張応
力が発生して、クラックが発生してしまう。That is, the coefficient of thermal expansion of quartz is 0.055 x 10
/(1eg, the coefficient of thermal expansion of silicon is 0.42×
10/deg, which is the melting temperature of silicon.
When the temperature changes from 420° C. to room temperature, tensile stress occurs in the silicon layer and cracks occur.

また、前述のような問題は、石英基板上に多結晶シ９　
”ンヲ小さくバターニングした後、レーザによって再結
晶させるアイランドエピタキシィと呼ばれる方法にも当
てはまシ、内部応力の存在によるキャリア移動度の低下
という問題があった。In addition, the above-mentioned problem arises when polycrystalline silicon is placed on a quartz substrate.
``This also applies to a method called island epitaxy, in which small patterns are formed and then recrystallized using a laser, and there is a problem in that the carrier mobility decreases due to the presence of internal stress.

この発明は、前述した問題を解決しようとするもので、
石英基板のような絶縁物基板上にシリコン素子能動層の
ような半導体素子能動層を形成するときに、この能動層
中に発生する内部応力を小さくするため、絶縁物基板と
前記能動層との間にポリシリコンなどからなる半導体薄
膜と、シリコン酸化膜などの絶縁膜とを形成しておくこ
とによシ、前記能動層の結晶品質を改善した半導体装置
・を提°供することを目的としている。This invention attempts to solve the above-mentioned problems.
When forming a semiconductor device active layer such as a silicon device active layer on an insulating substrate such as a quartz substrate, in order to reduce the internal stress generated in this active layer, the bond between the insulating substrate and the active layer is The object of the present invention is to provide a semiconductor device in which the crystal quality of the active layer is improved by forming a semiconductor thin film made of polysilicon or the like and an insulating film such as a silicon oxide film in between. .

以下、この発明の実施例につき図面を参照して説明する
。Embodiments of the invention will be described below with reference to the drawings.

第３図はこの発明の第１の実施例を示す。第３図におい
て、３１は透明な絶縁基板である石英基板、３２は石英
基板３１上に形成した半導体薄膜である多結晶シリコン
ノ臂ツファ層であシ、この／＃ツファ層３２紘０．２〜
２．０ミクロンの厚さである。FIG. 3 shows a first embodiment of the invention. In FIG. 3, 31 is a quartz substrate which is a transparent insulating substrate, and 32 is a polycrystalline silicon tuff layer which is a semiconductor thin film formed on the quartz substrate 31. ~
It is 2.0 microns thick.

３３は前記バッファ層３２上に形成した絶縁膜であるシ
リコン酸化膜であシ、この酸化膜３３は０．０５〜１．
０ミク四ンの厚さである。３４はシリコン酸化ＪＩＱ３
３上に形成した半導体素子能動層であるシリコン素子能
動層、３５はシリコン素子能動層３４上に形成した熱処
理用表面保護膜である。33 is a silicon oxide film which is an insulating film formed on the buffer layer 32, and this oxide film 33 has a thickness of 0.05 to 1.
It has a thickness of 0 micrometers. 34 is silicon oxide JIQ3
A silicon element active layer 35 is a semiconductor element active layer formed on the silicon element active layer 34, and a surface protection film 35 for heat treatment is formed on the silicon element active layer 34.

そして、シリコン素子能動層３４はシリコン酸化膜３３
上に形成した多結晶シリコンを溶融し、再結晶させたも
のである。The silicon element active layer 34 is formed by a silicon oxide film 33.
Polycrystalline silicon formed above is melted and recrystallized.

前述のように構成されたこの発明の第１の実施例の半導
体装置では、多結晶シリコンを溶融し、再結晶させてシ
リコン素子能動層を得るときに、この能動層の下に多結
晶シリコンバッファ層があるために、石英基板自体は、
シリコンの溶融温度まで温度が上昇しない。したがって
、これだけでも熱膨張の差による内部応力の発生を軽減
させることができる上に、前記バッファ層が存在してい
るため、熱膨張の差による内部応力がバッファ層とシリ
コン酸化膜、この酸化膜とシリコン能動層に分散され、
この能動層内の内部応力はパックア層、シリコン酸化膜
がない場合に比べて著しく減少させることができる。In the semiconductor device of the first embodiment of the present invention configured as described above, when polycrystalline silicon is melted and recrystallized to obtain a silicon element active layer, a polycrystalline silicon buffer is formed under this active layer. Because of the layers, the quartz substrate itself is
The temperature does not rise to the melting temperature of silicon. Therefore, this alone can reduce the occurrence of internal stress due to the difference in thermal expansion, and since the buffer layer is present, the internal stress due to the difference in thermal expansion can be reduced between the buffer layer and the silicon oxide film, and this oxide film. and dispersed in the silicon active layer,
The internal stress within this active layer can be significantly reduced compared to the case where there is no pack layer or silicon oxide film.

なお、バッファ層は、０．２ミクロン未満ではとれの熱
的歪の緩和作用が不十分であり、２．０ミクロンを超え
ると半導体装置の段差が著しくなって好ましくない。ま
た、シリコン酸化膜は０．０５ミク四ン未満ではこれと
バッファ層との熱的絶縁が不十分であ、６．ｉ、ｏミク
ロンを超えると能動層を形成するときにシリコン酸化膜
上の多結晶シリコンだけを溶融させ難くなって好ましく
ない。したかって、パックア層は０．２〜２．０ミクロ
ン、シリコン酸化膜は０．０５〜１．０電り四ンの範囲
の厚さ。It should be noted that if the buffer layer is less than 0.2 microns, the effect of alleviating the thermal strain of the chip is insufficient, and if it exceeds 2.0 microns, the level difference in the semiconductor device becomes significant, which is not preferable. In addition, if the silicon oxide film is less than 0.05 micrometers thick, thermal insulation between the silicon oxide film and the buffer layer is insufficient; If it exceeds i,0 microns, it becomes difficult to melt only the polycrystalline silicon on the silicon oxide film when forming the active layer, which is not preferable. Therefore, the thickness of the packua layer is in the range of 0.2 to 2.0 microns, and the thickness of the silicon oxide film is in the range of 0.05 to 1.0 microns.

に形成することが好ましい。It is preferable to form the

第４図はこの発明の第２の実施例を示す。第１の実施例
では、石英基板上の全面にわたって多結晶シリコンバッ
ファ層、シリコン酸化膜およびシリコン素子能動層を形
成したが、第２の実施例のように石英基板３１上のシリ
コン素子能動層３４を形成する部分にだけ、多結晶シリ
コンバッファ層３２、シリコン酸化膜３３および表面保
護膜３５を形成したものである。また、第５図はこの発
明の第３の実施例を示す。この実施例では、石英基板３
１上に形成した１つの多結晶シリコンバッフ７層３２お
よびシリコン酸化膜３３上に、複数のシリコン素子能動
層３４を設け、これらの上にそれぞれ表面保護膜３５を
形成したものである。そして、第２、第３の実施例でも
第１の実施例のもの呂同様な作用、効果が得られる。FIG. 4 shows a second embodiment of the invention. In the first embodiment, the polycrystalline silicon buffer layer, the silicon oxide film, and the silicon element active layer were formed over the entire surface of the quartz substrate, but as in the second embodiment, the silicon element active layer 34 on the quartz substrate 31 A polycrystalline silicon buffer layer 32, a silicon oxide film 33, and a surface protection film 35 are formed only in the portions where . Further, FIG. 5 shows a third embodiment of the present invention. In this embodiment, the quartz substrate 3
A plurality of silicon element active layers 34 are provided on one polycrystalline silicon buffer 7 layer 32 and a silicon oxide film 33 formed on the silicon oxide film 1, and a surface protection film 35 is formed on each of these layers. In the second and third embodiments, the same functions and effects as those of the first embodiment can be obtained.

なお、この発明において、半導体素子能動層をガリウム
−砒素から構成するなど、基板、パックア層の半導体膜
、絶縁膜の材質は適宜変更できる。In the present invention, the materials of the substrate, the semiconductor film of the packa layer, and the insulating film can be changed as appropriate, such as forming the semiconductor element active layer from gallium-arsenic.

以上説明したように、この発明の半導体装置は、絶縁基
板上に半導体薄膜と絶縁膜を介して半導体素子能動層を
設けたので、この能動層を形成するときの熱によシ発生
する能動層の内部応力を小さくすることができ、クラッ
クの発生を防止でき、その結晶品質を改善できるという
効果があシ、透明な絶縁基板を用いてこれの上に素子を
形成する表示素子のような半導体装置に利用することが
できる。As explained above, in the semiconductor device of the present invention, since the semiconductor element active layer is provided on the insulating substrate through the semiconductor thin film and the insulating film, the active layer is generated due to heat when forming the active layer. It has the effect of reducing internal stress, preventing the occurrence of cracks, and improving the crystal quality of semiconductors such as display elements that use a transparent insulating substrate and form elements on it. It can be used for equipment.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置を示す断面図、第２図は同内
部応力発生の説明図、第３図はこの発明の第１の実施例
による半導体装置を示す断面図、第４図および第５図は
同第２および第３の実施例による半導体装置をそれぞれ
示す断面図である。 １１・・・石英基板、１２・・・シリコン膜、１３・・
・クラック、１４・・・応力、３１・・・石英基板−３
２・・・多結晶シリコン層、３３・・・シリコン酸化膜
、３４・・・シリコン素子能動層、３５・・・表面保護
膜１、第１図 １２ 第２図 第４図 第５図 手続補疋書 昭和５８年５月２．０日 特許庁長官若杉和夫　殿 １、事件の表示 昭和５７年特許　　願第１０９７７０　　号２、発明の
名称 半導体装置 ３、補正をする者 事件との関係　　　　　特　許　出願人（０２９）沖電
気工業株式会社 ４、代理人 ５、補正命令の日付　　昭和　　年　　月　　日　（１
妬）６、補正の対象 明細書の発明の詳細な説明の欄 １７５FIG. 1 is a sectional view showing a conventional semiconductor device, FIG. 2 is an explanatory diagram of internal stress generation in the same, FIG. FIG. 5 is a cross-sectional view showing semiconductor devices according to the second and third embodiments, respectively. 11...Quartz substrate, 12...Silicon film, 13...
・Crack, 14...Stress, 31...Quartz substrate-3
2... Polycrystalline silicon layer, 33... Silicon oxide film, 34... Silicon element active layer, 35... Surface protection film 1, Figure 1 12 Figure 2 Figure 4 Figure 5 Procedure supplement Book dated May 2, 1980 Kazuo Wakasugi, Commissioner of the Japan Patent Office 1. Indication of the case 1989 Patent Application No. 109770 2. Name of the invention Semiconductor device 3. Relationship with the person making the amendment Patent application Person (029) Oki Electric Industry Co., Ltd. 4, Agent 5, Date of amendment order Showa year, month, day (1
6. Column 175 for detailed description of the invention in the specification subject to amendment

Claims (1)

【特許請求の範囲】[Claims] 絶縁物基板上に形成した半導体薄膜と、この半導体薄膜
上に形成した絶縁膜と、この絶縁膜上に形成した半導体
素子能動層とを備えたことを特徴とする半導体装置。A semiconductor device comprising: a semiconductor thin film formed on an insulating substrate; an insulating film formed on the semiconductor thin film; and a semiconductor element active layer formed on the insulating film.
JP10977082A 1982-06-28 1982-06-28 Semiconductor device Pending JPS59939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10977082A JPS59939A (en) 1982-06-28 1982-06-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10977082A JPS59939A (en) 1982-06-28 1982-06-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59939A true JPS59939A (en) 1984-01-06

Family

ID=14518783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10977082A Pending JPS59939A (en) 1982-06-28 1982-06-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59939A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60144931A (en) * 1984-01-07 1985-07-31 Agency Of Ind Science & Technol Manufacture of semiconductor device
JPS60189922A (en) * 1984-02-21 1985-09-27 エヌ・ベー・フイリツプス・フルーイランペンフアブリケン Method of producing single crystal layer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE ERECT DEU LETT=1980 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60144931A (en) * 1984-01-07 1985-07-31 Agency Of Ind Science & Technol Manufacture of semiconductor device
JPS60189922A (en) * 1984-02-21 1985-09-27 エヌ・ベー・フイリツプス・フルーイランペンフアブリケン Method of producing single crystal layer

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