JPS58155A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58155A JPS58155A JP9852781A JP9852781A JPS58155A JP S58155 A JPS58155 A JP S58155A JP 9852781 A JP9852781 A JP 9852781A JP 9852781 A JP9852781 A JP 9852781A JP S58155 A JPS58155 A JP S58155A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- resist
- groove
- manufacturing
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかシ、特に集積回路
の配線の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing wiring for an integrated circuit.
近年集積回路の集積度の向上は著しいものが有り、今後
もさらに向上することが予想される。それに伴ない配I
IO微細化及び多層構造が必須条件になってきている。In recent years, there has been a remarkable improvement in the degree of integration of integrated circuits, and further improvement is expected in the future. Accordingly, distribution I
IO miniaturization and multilayer structure are becoming essential conditions.
一般に金属配線を用いた集積回路の配線は層間絶縁物の
上に蒸着方法を用いた金属層を形成し。Generally, integrated circuit wiring using metal wiring involves forming a metal layer on an interlayer insulator using a vapor deposition method.
配1mパターンをマスクによるエツチング技術を使って
行なう。A 1 m pattern is etched using a mask etching technique.
従来の配線製造方法を図を用いて異体的に説明する。第
1!lは一般に金属を配線に用い九場合の集積回路の配
線断面図である。シリコン基板41上に酸化シリコン膜
12などの配線層間絶縁物を設け、その上に金層配線部
13を設置ている。同図において配線層間絶縁物12の
上に金属層13を形成する方法社命後O集積度の向上に
不利である。それは高集積度による金属配線の多層化を
考えた場合に、下層の金属部と眉間絶縁部の段差を上層
の金属配線が横断する時にこの上層の金属配線が段切れ
を起こす原因となる。このように層間絶縁部の上に金属
層を形成する製造方法でれ1次の配線層の段切れを誘発
し、集積回路の製造に大きな支障をきたす。A conventional wiring manufacturing method will be explained in detail using figures. 1st! 1 is a wiring cross-sectional view of an integrated circuit in which metal is generally used for the wiring. A wiring interlayer insulator such as a silicon oxide film 12 is provided on a silicon substrate 41, and a gold layer wiring portion 13 is provided thereon. In the figure, the method of forming the metal layer 13 on the wiring interlayer insulator 12 is disadvantageous in improving the degree of O integration. When considering multi-layer metal wiring due to high integration, when the upper layer metal wiring crosses the step between the lower metal part and the glabellar insulation part, this causes the upper layer metal wiring to break. As described above, the manufacturing method in which a metal layer is formed on an interlayer insulating portion causes disconnection of the primary wiring layer, which causes a major problem in the manufacturing of integrated circuits.
本発明の目的は絶縁膜上に形成された金属配線部とこの
金属配線の上にある層間絶縁物によって形成される段差
を無くすことのできる半導体装置の製造方法を提供する
ものである。SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device that can eliminate a step formed by a metal wiring portion formed on an insulating film and an interlayer insulator on the metal wiring.
上記目的を達成するために本発明の製造方法は、層間絶
縁物上に溝を作りそこに金属配線を敷くととKより段差
を無くすことを特徴とするものである。In order to achieve the above object, the manufacturing method of the present invention is characterized in that when a groove is formed on an interlayer insulator and a metal wiring is laid there, there is no difference in level.
次に図を用いて本発明の実施例の製造方法を説明する。Next, a manufacturing method according to an embodiment of the present invention will be explained using the drawings.
第2図(a)Fi金属配線パターンにそって層間絶縁物
を深さ0.5μmにエツチングした図である。図で21
はシリコン基板であシ%22は1.0μmの二酸化シリ
コンの層間絶縁物である0次に第2図(b)は層間絶縁
物上に真空蒸着方法により0.5μmのアルミの金属層
23を形成し、その上にフォトレジスト24を3000
回転/毎分で回転法によシ塗布した図である。この時エ
ツチング開孔上のアルミ上のレジストは厚く、他の周辺
のアルミ上には薄く形成される。続く第2図(C)はこ
の開孔上の金属配線部の7オトレジストの厚さと周辺部
の7オトレジストの厚さの違いを利用して周辺金属部が
表面に出るまでフォトレジスト24を現俸液によシエ、
チングしたものである。?:、0レジストのエツチング
は例えばフレオンガスによるプラズマエッチ”t’4!
い、1に2図(d)はこのフォトレジストをマスクにし
て周辺金属部をプラズマエツチングするととKよシ得ら
れた金属配線の断面図である。FIG. 2(a) is a diagram in which the interlayer insulator is etched to a depth of 0.5 μm along the Fi metal wiring pattern. 21 in figure
is a silicon substrate, %22 is a 1.0 μm silicon dioxide interlayer insulator, and FIG. 2(b) shows a 0.5 μm aluminum metal layer 23 on the interlayer insulator by vacuum deposition. A photoresist 24 with a thickness of 3000 nm is formed on the photoresist 24.
It is a figure which applied by the rotation method at rotation/min. At this time, the resist on the aluminum above the etching hole is thick, and the resist on the other peripheral aluminum is thin. Next, in FIG. 2 (C), the photoresist 24 is applied until the peripheral metal part comes out to the surface, taking advantage of the difference in the thickness of the 7th photoresist on the metal wiring part above this opening and the thickness of the 7th photoresist on the peripheral part. liquid,
It is a tinged one. ? :, 0 resist etching is, for example, plasma etching using Freon gas "t'4!"
Figures 1 and 2 (d) are cross-sectional views of metal wiring obtained by plasma etching the peripheral metal parts using this photoresist as a mask.
以上述べたように本発明の製造方法を使えば従来方法に
比べて金属配線によ〕形成される段差を無くシ、高集積
度に伴なう多層構造を可能にする。As described above, the manufacturing method of the present invention eliminates the step difference formed by metal wiring compared to the conventional method, and enables a multilayer structure associated with a high degree of integration.
さらに本発明の特徴として従来性なっている手法で製造
することが可能である。Furthermore, a feature of the present invention is that it can be manufactured using conventional methods.
第1図は従来の製造方法による集積回路の配線断面図で
あシ、第2図は本発明の実施例の製造方法を工租順に示
す断面図である。
尚1図において、11.21−・・・・・シリコン基板
、12.22・・・・・・配線層間絶縁物、13.23
・−・・・・金属配線、24−°・・・フォトレジスト
である。
羊 2 凹FIG. 1 is a cross-sectional view of the wiring of an integrated circuit according to a conventional manufacturing method, and FIG. 2 is a cross-sectional view showing the manufacturing method of an embodiment of the present invention in order of construction. In Fig. 1, 11.21-... silicon substrate, 12.22... wiring interlayer insulator, 13.23
・-・・Metal wiring, 24-° ・・Photoresist. sheep 2 concave
Claims (1)
する工程と、該絶縁物上に導電層を形成し、皺導電層上
にレジストを形成する工程と、該絶縁物の溝上の皺導電
層上にのみレジストを残す工程と、該残余せるレジスト
をマスクとして該溝内の導電層以外の導電層の部分をエ
ツチングする工程とを有する事を特徴とする半導体装置
の製造方法。forming an insulating layer on a substrate; forming a groove in the insulating layer; forming a conductive layer on the insulator; forming a resist on the wrinkled conductive layer; A method for manufacturing a semiconductor device, comprising the steps of: leaving a resist only on the wrinkled conductive layer; and using the remaining resist as a mask, etching a portion of the conductive layer other than the conductive layer in the groove.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9852781A JPS58155A (en) | 1981-06-25 | 1981-06-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9852781A JPS58155A (en) | 1981-06-25 | 1981-06-25 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58155A true JPS58155A (en) | 1983-01-05 |
Family
ID=14222137
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9852781A Pending JPS58155A (en) | 1981-06-25 | 1981-06-25 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58155A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6074456A (en) * | 1983-06-16 | 1985-04-26 | デイジタル イクイプメントコ−ポレ−シヨン | Pattern disposed with recess by anisotropic reactive ion etching and high density multilayer metallized integrated circuit designed thereby |
-
1981
- 1981-06-25 JP JP9852781A patent/JPS58155A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6074456A (en) * | 1983-06-16 | 1985-04-26 | デイジタル イクイプメントコ−ポレ−シヨン | Pattern disposed with recess by anisotropic reactive ion etching and high density multilayer metallized integrated circuit designed thereby |
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