JPS5813998B2 - memory device - Google Patents
memory deviceInfo
- Publication number
- JPS5813998B2 JPS5813998B2 JP53153366A JP15336678A JPS5813998B2 JP S5813998 B2 JPS5813998 B2 JP S5813998B2 JP 53153366 A JP53153366 A JP 53153366A JP 15336678 A JP15336678 A JP 15336678A JP S5813998 B2 JPS5813998 B2 JP S5813998B2
- Authority
- JP
- Japan
- Prior art keywords
- drain
- circuit
- memory
- field effect
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Description
【発明の詳細な説明】 本発明はスタティック形のメモリ装置に関する。[Detailed description of the invention] The present invention relates to a static type memory device.
スタティック形のメモリ装置に使用するメモリ回路とし
て、従来、第１図にて全体としてＵで示す如き、ドレイ
ンが負荷Ｌ１に、ソースが接地に夫々接続せる例えばｎ
チャンネル型のＭＩＳ電界効果型トランジスタ（以下簡
単の為トランジスタと称す）Ｑ１と、ドレインが負荷Ｌ
２及びトランジスタＱ１のゲートに、ソースが接地に、
ゲートがトランジスタＱ１のトレインに接続せるｎチャ
ンネル型のトランジスタＱ２と、ドレイン及びソースの
何れか一方がトランジスタＱ１のドレイン及び負荷Ｌ１
の接続中点Ｐ１に、他方が書込・読出用線（以下ビット
線と称す）Ｂ１ に、ゲートが制御用線（以下ワード線
と称す）Ｗに夫々接続せるｎチャンネル型のトランジス
タＱ３と、ドレイン及びソースの何れか一方がトランジ
スタＱ２のドレイン及び負荷Ｌ２の接続中点Ｐ２に、他
方が他のビット線Ｂ１’に、ゲートがワード線Ｗに夫々
接続せるｎチャンネル型のトランジスタＱ４とを具備し
、而してこの場合負荷Ｌ１及びＬ２のトランジスタＱ１
及びＱ２側が電源線路Ｆを介して正極性の電源端子ＶＤ
に接続されてなる構成のものが提案されている。Conventionally, as a memory circuit used in a static type memory device, the drain is connected to the load L1 and the source is connected to the ground, for example n, as shown overall by U in FIG.
A channel type MIS field effect transistor (hereinafter referred to as a transistor for simplicity) Q1 and a drain connected to a load L
2 and the gate of transistor Q1, the source is grounded,
An n-channel transistor Q2 whose gate is connected to the train of the transistor Q1, and whose drain and source are connected to the drain of the transistor Q1 and the load L1.
an n-channel type transistor Q3 whose other side is connected to the connection midpoint P1, whose other side is connected to a write/read line (hereinafter referred to as a bit line) B1, and whose gate is connected to a control line (hereinafter referred to as a word line) W; It is equipped with an n-channel transistor Q4 whose drain and source are connected to the connection midpoint P2 between the drain of the transistor Q2 and the load L2, the other to the other bit line B1', and whose gate is connected to the word line W. However, in this case, the transistor Q1 of the loads L1 and L2
and the Q2 side is connected to the positive power supply terminal VD via the power supply line F.
A configuration has been proposed in which the
尚本例に於では負荷Ｌ１がドレイン及びゲートを電源線
路Ｆに、ソースをトランジスタＱ１のドレインに接続せ
るトランジスタＱ５でなり、又負荷Ｌ２が同様にドレイ
ン及びゲ−トを電源線路Ｆに、ソースをトランジスタＱ
２のドレインに接続せるトランジスタＱ６でなる場合が
示されている。In this example, the load L1 is a transistor Q5 whose drain and gate are connected to the power supply line F and whose source is connected to the drain of the transistor Q1, and the load L2 is similarly connected to the power supply line F and its source. The transistor Q
A case is shown in which the transistor Q6 is connected to the drain of the transistor Q6.
又斯るメモリ回路を使用したメモリ装置として第２図に
示す如き、複数Ｍ×Ｎ個のメモリ回路Ｕｌｌ ｔ ＵＩ
２・・・・・・・・・Ｕ１Ｎ；Ｕ２，，Ｕ２・・・・・
・・・・・Ｕ２ Ｎ＋・・・・・・・・・ＵＭｌ ＋
ＵＭ２・・・・・・・・・ＵＭＮと、複数Ｍ本のワード
線Ｗ１，Ｗ２・・・・・・・・・ＷＭと、複数Ｎ対のビ
ット線Ｂ１及びＢ１′，Ｂ２及びＢ２′，・・・・・・
・・・ＢＮ及び及びＢ／と、複数Ｎ本の電源線Ｆ１，Ｆ
２・・・・・・・・・ＦＮとを具備し、而してこの場合
メモリ回路Ｕ１１（ｉ＝１，２・・・・・・・・・Ｍ，
ｊ＝１．２・・・・・・・・・Ｎ）が、第１図のメモリ
回路Ｕと同様の構成を有し、但しメモリ回路Ｕｉ のト
ランジスタＱ３のドレイン及びソースの他方がビツド線
Ｂｊに、ゲートがワード線Ｗｉに夫々接続され、メモリ
回路ＵｉｉのトランジスタＱ４のドレイン及びソースの
他方がビット線Ｂ′に、ゲートがワード線Ｗ，に夫々接
続され、メモリ回路Ｕｉｉの負荷Ｌ１及びＬ２のトラン
ジスタＱ１及びＱ２側とは反対側が電源線路Ｆを介して
正極性の電源端子ＶＤに接続され、一方ビット線Ｂｉ及
びＢ！が充電用回路Ｄｉ、及び入力回路Ｈ１及び出力回
路Ｈ２を接続せる選択接続回路Ｇに接続されてなる構成
のものが提案されている。Further, as a memory device using such a memory circuit, a plurality of M×N memory circuits UlltUI as shown in FIG.
2......U1N;U2,,U2...
...U2 N+...UMl +
UM2......UMN, a plurality of M word lines W1, W2...WM, and a plurality of N pairs of bit lines B1 and B1', B2 and B2',・・・・・・
...BN and and B/ and a plurality of N power supply lines F1, F
2...FN, and in this case, the memory circuit U11 (i=1, 2...M,
j=1.2...N) has the same configuration as the memory circuit U in FIG. 1, except that the other of the drain and source of the transistor Q3 of the memory circuit Ui is connected to the bit line Bj. The gates are connected to the word line Wi, the other of the drain and source of the transistor Q4 of the memory circuit Uii is connected to the bit line B', the gate is connected to the word line W, and the loads L1 and L2 of the memory circuit Uii are connected to the word line Wi. The side opposite to the transistors Q1 and Q2 of the transistors Q1 and Q2 is connected to the positive polarity power supply terminal VD via the power supply line F, while the bit lines Bi and B! A configuration has been proposed in which the charging circuit Di is connected to a selection connection circuit G that connects the input circuit H1 and the output circuit H2.
尚本例に於ては充電回路Ｄｉがドレインが電源端子ＶＤ
に、ソースがビット線Ｂ に、ゲートがクロックパルス
源Ｋに夫々接続せるトランジスタＱ７と、ドレインが電
源端子ＶＤに、ソースがビット線Ｂ ′，に、ゲートが
クロツクパルス源Ｋに夫々接続せるトランジスタＱ８と
を以って構成されている場合が示されている。In this example, the drain of the charging circuit Di is the power supply terminal VD.
, a transistor Q7 whose source is connected to the bit line B, a gate connected to the clock pulse source K, and a transistor Q8 whose drain is connected to the power supply terminal VD, the source is connected to the bit line B', and the gate is connected to the clock pulse source K. A case is shown in which the system is configured with the following.
所で第２図に示されているメモリ装置によれば、以下述
べる機能が得られるものである。According to the memory device shown in FIG. 2, the following functions can be obtained.
即ちクロツクパルス源Ｋより第３図Ａに示す如き周期Ｔ
。That is, the clock pulse source K generates a period T as shown in FIG. 3A.
.
を有する負極性のクロツクパルス列ＣＰを得、而してワ
ード線Ｗｉに第３図Ｂに示す如きクロツクパルス列ＣＰ
の一のパルスの得られる周期Ｔｋに於てその期間Ｔｋの
頭初の時点ｔ１又はこれより僅かに遅れた時点より期間
Ｔｋの終りの時点ｔ３又はこれより僅かに遅れた時点迄
の区間Ｔｗに於て高レベルをとるクロツクパルス列ＣＰ
と同期せる正極性の制御パルスＷＰ１を与え、又ビット
線Ｂｉ（又はＢ′・）に入力回路Ｈ１及び選択接続回路
Ｇを介して第３図Ｃに示す如きクロックパルス列ＣＰの
一のパルスの得られる期間Ｔｋに於ける制御パルスＷＰ
ｉの得られる時点より遅れた時点ｔ２より期間Ｔｋの終
りの時点ｔ３迄の区間ＴＢに於て低レベルをとる負極性
の書込パルスＢＰｉ（又はＢＰ／ ）を与えるものとす
れば、ビット線Ｂｉ及びＢ′，と接地との間の浮遊容量
Ｃｊ及びＣ′，が、期間Ｔｋの前及び後に於て充電用回
路ＤｊのトランジスタＱ７及びＱ８がオンであることに
より、電源端子ＶＤよりの正極性の電源にて充電され、
又浮遊容量Ｃ （又はＣ′・）が、期間ＴＢの前后に於
てビット線Ｂｊ （又はＢ勺に入力回路Ｈ１及び選択接
続回路Ｇを介して高レベルが与えられていることにより
、選択接続回路Ｇ側より充電され、更に浮遊容量Ｃ’（
又はＣｉ）が、期間ＴＢの前后を問わずビット線Ｂ’（
又はＢｉ）に入力回路Ｈ１及び選択接続回路Ｇを介して
高レ１ベルが与えられていることにより、選択接続回路
Ｇ側より充電されるものであるが、期間Ｔｋに於ける制
御パルスＷＰｉが高レベルの区間をとる期間に於てメモ
リ回路ＵｉｉのトランジスタＱ３及びＱ４がオンとなり
、一方ビット線Ｂｉ（又はＢ′）に入力回路Ｈ１及び選
択接続回路Ｇを介して低レベルが与えられることにより
、期間ＴＢに於て浮遊容量Ｃｉ（又はＣ′）の充電電荷
が選択接続回路Ｇ側に放電し、この為期間ＴＢに於てメ
モリ回路ＵＩｊの接続中点Ｐ１が強制的に低レベルとな
つてメモリ回路ＵｉｉのトランジスタＱ２（又はＱｌ）
がオフ、これに応じてトランジスタＱｌ（又はＱ２）が
オンとなり、そしてその状態が期間ＴＢを過ぎても２値
表示で例えば「１」の情報として維持され、斯くてメモ
リ回路Ｕｉｉへの情報「１」の書込がなされることとな
るものである。A negative polarity clock pulse train CP is obtained, and a clock pulse train CP as shown in FIG. 3B is applied to the word line Wi.
In the period Tk in which one pulse is obtained, in the interval Tw from the beginning of the period Tk, the first time t1, or a time slightly later than this, to the end of the period Tk, the time t3, or a time slightly later than this. The clock pulse train CP takes a high level at
A control pulse WP1 of positive polarity is applied to the bit line Bi (or B'. Control pulse WP during period Tk
If we apply a negative polarity write pulse BPi (or BP/) that takes a low level in the interval TB from time t2, which is later than the time when i is obtained, to time t3, which is the end of period Tk, the bit line Since the transistors Q7 and Q8 of the charging circuit Dj are on before and after the period Tk, the stray capacitances Cj and C' between Bi and B' and the ground are connected to the positive terminal from the power supply terminal VD. It is charged with a natural power source,
In addition, the stray capacitance C (or C') is caused by the selective connection because a high level is applied to the bit line Bj (or Bj) via the input circuit H1 and the selection connection circuit G before and after the period TB. It is charged from the circuit G side, and the stray capacitance C'(
or Ci) is bit line B'(
Or Bi) is given a high level 1 via the input circuit H1 and the selection connection circuit G, so that it is charged from the selection connection circuit G side, but the control pulse WPi in the period Tk is During the high level period, transistors Q3 and Q4 of the memory circuit Uii are turned on, while a low level is applied to the bit line Bi (or B') via the input circuit H1 and the selection connection circuit G. , during the period TB, the charge of the stray capacitance Ci (or C') is discharged to the selective connection circuit G side, and therefore the connection midpoint P1 of the memory circuit UIj is forced to a low level during the period TB. Transistor Q2 (or Ql) of memory circuit Uii
is off, the transistor Ql (or Q2) is turned on in response to this, and even after the period TB has passed, the state is maintained as information "1" in a binary display, and thus the information "1" is sent to the memory circuit Uii. 1" will be written.
又斯る状態より、クロックパルス源Ｋより第３図Ａに示
す如きクロツクパルス列ＣＰを得、而してワード線Ｗｉ
に第３図Ｂに示す如き制御パルスＷＰｉを与え、更にビ
ット線Ｂｉ（又はＢ′・）を第３図Ｃにて上述せる書込
パルスＴＢの期間ＴＢと同じ期間に於て選択接続回路Ｇ
を介して出力回路Ｈ２に接続するものとすれば、期間Ｔ
ｋに於ける制御パルスＷＰｉが高レベルをとる区間に於
てメモリ回路ＵｉｊのトランジスタＱ３及びＱ４がオン
となり、この場合メモリ回路ＵｉｊのトランジスタＱ１
（又はＱ２）がオン、トランジスタＱ２（又はＱｌ）
がオンであることにより、浮遊容量Ｃｉ（又はＣ１）の
充電電荷がトランジスタＱ３（又はＱ４）及びＱ１（又
はＱ２）を通じて接地に放電し、この為期間ＴＢに於て
ビット線Ｂｉ（又はＢ１）が低レベルとなり、そしてそ
れが選択接続回路Ｇを介して出力回路Ｈ２にてメモリ回
路Ｕｉｊの情報が「１」であるとして読出され、斯くて
メモリ回路Ｕｉｊの「１」の情報の読出しがなされるこ
ととなるものである。Also, from this state, a clock pulse train CP as shown in FIG. 3A is obtained from the clock pulse source K, and the word line Wi
A control pulse WPi as shown in FIG. 3B is applied to the bit line Bi (or B'), and the selection connection circuit G is applied to the bit line Bi (or B') in FIG.
If the connection is made to the output circuit H2 via the period T
In the period in which the control pulse WPi takes a high level at k, transistors Q3 and Q4 of the memory circuit Uij are turned on, and in this case, the transistor Q1 of the memory circuit Uij is turned on.
(or Q2) is on, transistor Q2 (or Ql)
is on, the charge in the stray capacitance Ci (or C1) is discharged to the ground through the transistors Q3 (or Q4) and Q1 (or Q2), and therefore the bit line Bi (or B1) is turned on during the period TB. becomes a low level, and the information in the memory circuit Uij is read as "1" at the output circuit H2 via the selection connection circuit G, and thus the information "1" in the memory circuit Uij is read out. This is something that will happen.
尚上述せるメモリ回路Ｕｉｉへの情報「１」の書込がな
されて居らずメモリ回路ＵｉｊのトランジスタＱ１（又
はＱ２）がオフ、トランジスタＱ２（又はＱ１）がオン
である場合は、メモリ回路Ｕｉｊに情報「０１の書込が
なされていることを意味し、又斯る状態より上述せる読
出しをなせば、浮遊容量Ｃｉ（又はＣ１）の充電電荷が
メモリ回路Ｕｉ，のトランジスタＱｌ（又はＱ２）のオ
フの為に放電されず、従って期間ＴＢに於てビット線Ｂ
ｊ （又はＢ′ｊ）が低レベルとなることはなく、従っ
て出力回路Ｈ２にてメモリ回路Ｕｉｉの情報が「０」で
あるとして読出されるものである。Note that if the information "1" is not written to the memory circuit Uii described above and the transistor Q1 (or Q2) of the memory circuit Uij is off and the transistor Q2 (or Q1) is on, the memory circuit Uij is This means that the information "01" has been written, and if the above reading is performed from such a state, the charge in the stray capacitance Ci (or C1) will be transferred to the transistor Ql (or Q2) of the memory circuit Ui. The bit line B is not discharged because it is off, and therefore the bit line B is not discharged during the period TB.
j (or B'j) never becomes a low level, and therefore the information in the memory circuit Uii is read as "0" by the output circuit H2.
然し乍ら第２図に示されている従来のメモリ回路の場合
、そのメモリ回路ＵｉｉのトランジスタＱ１及びＱ２の
負荷Ｌ１及びＬ２のトランジスタＱ１及びＱ２側とは反
対側が、電源線路Ｆ を介して電源端子ＶＤに接続され
ていることにより、上述せるメモリ機能が得られる様に
なされている為、メモリ回路Ｕｉｉの負荷Ｌ１及びＬ２
及び電源端子ＶＤ間に電源線路Ｆｉを要するものである
。However, in the case of the conventional memory circuit shown in FIG. 2, the sides of the loads L1 and L2 of the transistors Q1 and Q2 of the memory circuit Uii opposite to the transistors Q1 and Q2 side are connected to the power supply terminal VD via the power supply line F. Since the above-mentioned memory function is obtained by being connected to the memory circuit Uii, the loads L1 and L2 of the memory circuit Uii are
A power supply line Fi is required between the power supply terminal VD and the power supply terminal VD.
この為従来のメモリ装置は、それを所謂半導体モノリシ
ックに半導体集積化して構成するものとした場合、その
構成を高密度、小型化するに一定の限度を有したという
欠点を有していたものである。For this reason, conventional memory devices had the drawback that when they were constructed by integrating semiconductors into a so-called semiconductor monolith, there were certain limitations in achieving high density and miniaturization of the structure. be.
依って本発明は上述せる欠点のない新規なメモリ装置を
提案せんとするもので、以下詳述する所より明らかとな
るであろう。Therefore, the present invention seeks to propose a novel memory device free from the above-mentioned drawbacks, which will become clear from the detailed description below.
第４図は本発明によるメモリ装置に使用するメモリ回路
の一例を示し、第１図との対応部分には同一符号を附し
詳細説明はこれを省略するも、第１図にて上述せる構成
に於てその負荷Ｌ１及びＬ２のトランジスタＱ１及びＱ
２側とは反対側が電源線Ｆを介して電源端子ＶＤに接続
されているに代え、ビット線Ｂｌ’に接続されているこ
とを除いては第１図の場合と同様の構成を有する。FIG. 4 shows an example of a memory circuit used in the memory device according to the present invention. Parts corresponding to those in FIG. The transistors Q1 and Q of its loads L1 and L2 in
The configuration is the same as that in FIG. 1, except that the side opposite to the second side is connected to the bit line Bl' instead of being connected to the power supply terminal VD via the power line F.
又第５図は第４図に示されているよるメモリ回路Ｕを使
用した本発明によるメモリ装置の一例を示し、第２図と
の対応部分には同一符号を附し詳細説明はこれを省略す
るも、第２図にて上述せる構成に於て複数Ｎ本の電源線
Ｆ１〜ＦＮが省略され、又メモリ回路Ｕｉ，が第４図の
メモリ回路Ｕと同様の構成を有し、而してそのメモリ回
路Ｕｉｊの負荷ＬＩ及びＬ２のトランジスタＱ１及びＱ
２側とは反対側が電源線Ｆｊを介して電源端子ＶＤに接
続されているに代え、今Ｍが奇数であるものとすれ？メ
モリ回路Ｕ１１，Ｕ３１・・・・・・・・・ＵＭｔ ’
Ｕ１，Ｕ３・・・・・・・・・ＵＭ２’・・・・・・
・・・” Ｉ Ｎ＋ Ｕ３Ｎ・・・・・・・・・ＵＭＮ
の負荷Ｌ１及びＬ２のトランジスタＱ１及びＱ２側とは
反対側が夫々ビット線Ｂ′． ； Ｂ′， ；・・・・
・・・・・Ｂ′Ｎに、メモリ回路Ｕ２１， Ｕ４，・・
・・・・・・・Ｕ（Ｍ−＋）ｔ’ＵＵ ・・・・・・
・・・Ｕ ゛ ・・・・・・ｉ； Ｕ２Ｎ ，２
２フ ４２ （Ｍ−１）２ ”Ｕ４Ｎ・
・・・・・・・・Ｕ（Ｍ−＋）Ｎの負荷Ｌ１及びＬ２の
トランジスタＱ１及びＱ２側とは反対側が夫々ビット線
Ｂ１； Ｂ２；・・・・・・・・・ＢＮに夫々接続され
ていることを除いては第２図の場合と同様の構成を有す
る。Further, FIG. 5 shows an example of a memory device according to the present invention using the memory circuit U shown in FIG. 4, and corresponding parts to those in FIG. However, in the configuration described above in FIG. 2, the plurality of N power supply lines F1 to FN are omitted, and the memory circuit Ui has the same configuration as the memory circuit U in FIG. The load LI of the memory circuit Uij and the transistors Q1 and Q of L2
Suppose that the side opposite to the second side is connected to the power terminal VD via the power line Fj, and that M is an odd number. Memory circuits U11, U31...UMt'
U1, U3...UM2'...
・・・” I N+ U3N・・・・・・・・・UMN
The opposite sides of the loads L1 and L2 from the transistors Q1 and Q2 are respectively connected to the bit lines B'. ；B′、；・・・・
...B'N has memory circuits U21, U4,...
・・・・・・U(M-+)t'UU ・・・・・・
・・・U ゛ ・・・・・・i; U2N ,2
2F 42 (M-1)2 ”U4N・
・・・・・・The opposite sides of the transistors Q1 and Q2 of the loads L1 and L2 of U(M−+)N are respectively connected to the bit lines B1; B2; ・・・・・・・・・BN. It has the same configuration as the case in FIG. 2 except that it is shown in FIG.
以上で本発明によるメモリ装置の一例構成が明らかとな
ったが、斯るメモリ装置の構成によれば、第２図のメモ
リ装置につき前述せると同様のメモリ機能を得ることが
出来るものである。The configuration of one example of the memory device according to the present invention has been clarified above, and according to the configuration of such a memory device, it is possible to obtain the same memory function as described above with respect to the memory device of FIG. 2.
即ち、第５図のメモリ装置の構成によれば、そ？が第２
図にて上述せる構成に於てそのメモリ回路Ｕｉｊの負荷
Ｌ１及びＬ２のトランジスタＱ１及びＱ２側とは反対側
が電源線Ｆｉを介して電源端子ＶＤに接続されているに
代え、メモリ回路Ｕ，１，Ｕ３１・・・・・・・・・Ｕ
Ｍ１；Ｕ，２，Ｕ３。That is, according to the configuration of the memory device shown in FIG. is the second
In the configuration described above in the figure, instead of the sides of the loads L1 and L2 of the memory circuit Uij opposite to the transistors Q1 and Q2 being connected to the power supply terminal VD via the power supply line Fi, the memory circuits U, 1 , U31......U
M1; U, 2, U3.
・・・・・・・・・ＵＭ２；・・・・・・・・・；ＵＩ
ＮＩＵ３Ｎ・・・・・・・・・ＵＭＮの負荷Ｌ１及びＬ
２のトランジスタＱ１及びＱ２側とは反対側が夫々ビツ
ト線Ｂ］’ ； Ｂ２’ ；・・・・・・・・・；ＢＮ
′に接続され、又メモリ回路Ｕ２１，Ｕ４Ｉ・・・・・
・・・・Ｕ（Ｍ−１）１ ； Ｕ２２ １Ｕ４・・・・
・・・・・Ｕ（Ｍ−１）２ ’・・・・・・・・・：
Ｕ２Ｎ ｔ Ｕ４Ｎ・・・・・・・・・Ｕ（Ｍ−ｔ）Ｎ
の負荷Ｌ１及びＬ２のトランジスタＱ１及びＱ２側とは
反対側が夫々ビット線Ｂ，；）Ｂ２・・・・・・・・・
ＢＮに夫々接続されていることを除いては第２図の場合
と同様であるので、メモリ回路ＵｉｊのトランジスタＱ
１のゲート容量と負荷Ｌ２のインピーダンスとによる時
定数、及びトランジスタＱ２のゲート容量と負荷Ｌ１の
インピーダンスとによる時定数が、クロツクパルス源Ｋ
より得られる第３図Ａにて上述せるクロツクパルスＣＰ
の周期Ｔ。・・・・・・・・・UM2；・・・・・・・・・；UI
NIU3N......UMN loads L1 and L
The sides opposite to the transistors Q1 and Q2 of 2 are the bit lines B]';B2';
', and also memory circuits U21, U4I...
...U(M-1)1; U22 1U4...
・・・・・・U(M-1)2'・・・・・・・・・：
U2N t U4N・・・・・・U(M-t)N
The opposite sides of the loads L1 and L2 from the transistors Q1 and Q2 are the bit lines B, ;)B2, respectively.
The transistor Q of the memory circuit Uij is the same as the case of FIG. 2 except that it is connected to the BN respectively.
The time constant due to the gate capacitance of the transistor Q1 and the impedance of the load L2, and the time constant due to the gate capacitance of the transistor Q2 and the impedance of the load L1 are determined by the clock pulse source K.
The clock pulse CP mentioned above in FIG. 3A obtained by
period T.
に比し大である（２倍程度以上大であるを可とする）様
に例えば負荷Ｌ１及びＬ２のインピーダンスを予め選ん
で置けば、又周期Ｔ。For example, if the impedances of the loads L1 and L2 are selected in advance so that they are larger than the period T (permissible to be about twice as large), the period T.
及びＴｋがＴｋ／Ｔｏく１なる関係を有していれば、第
２図にて上述せる場合と同様に、クロツクパルス源Ｋよ
り第３図Ａに示す如きクロツクパルス列ＣＰを得、而し
てワード線Ｗｉに第３図Ｂに示す如き制御パルスＷＰｉ
を与え、又ビット線Ｂｉ（又はＢ′ｉ）に第３図Ｃに示
す如き期間ＴＢに於て低レベルをとる書込パルスＢＰｉ
（又はＢＰ’ｊ）を与えるものとすることにより、第２
図にて上述せる場合と同様にビット線Ｂｉ及びＢ／と接
地との間の浮遊容量Ｃｉ及びＣ′ｉが期間Ｔｋの前后に
於て電源端子ＶＤよりの電源により充電され、浮遊容量
Ｃｉ（又はＣ′ｉ）が期間ＴＢの前后に於て選択接続回
路Ｇ側より充電され、浮遊容量Ｃ′（又はＣｉ ）が期
間ＴＢの前后を問わず選択接続回路Ｇ側より充電される
ものであるが、第２図にて上述せる場合と同様に期間Ｔ
ｋに於ける制御パルスＷＰｉが高レベルをとりメモリ回
路ＵｉｉのトランジスタＱ３及びＱ４がオンとなり、一
方第２図にて上述せる場合と同様に周期ＴＢに於てビッ
ト線Ｂｉ（又はＢ′ｉ）が低レベルとなることにより期
間ＴＢに於て浮遊容量Ｃｊ （又はＣ′ｉ ）の充電電
荷が選択接続回路側に放電し、この為期間ＴＢに於て第
２図の場合と同様にトランジスタＱ１（又はＱ２）がオ
ンとなり、その状態が情報「１」として維持され、斯く
てメモリ回路Ｕｉｉへの情報「１」の書込がなされるこ
ととなるものである。If Tk and Tk have the relationship Tk/To less 1, the clock pulse train CP as shown in FIG. 3A is obtained from the clock pulse source K, as in the case described above with reference to FIG. A control pulse WPi as shown in FIG. 3B is applied to the word line Wi.
and a write pulse BPi which takes a low level on the bit line Bi (or B'i) during a period TB as shown in FIG. 3C.
(or BP'j), the second
Similarly to the case described above in the figure, the stray capacitances Ci and C'i between the bit lines Bi and B/ and the ground are charged by the power from the power supply terminal VD before and after the period Tk, and the stray capacitances Ci ( Or C'i) is charged from the selective connection circuit G side before and after the period TB, and the stray capacitance C' (or Ci) is charged from the selective connection circuit G side regardless of before and after the period TB. However, as in the case described above in Fig. 2, the period T
The control pulse WPi at time k takes a high level and transistors Q3 and Q4 of the memory circuit Uii are turned on, while at period TB the bit line Bi (or B'i) turns on, as in the case described above in FIG. As a result, during the period TB, the charge in the stray capacitance Cj (or C'i) is discharged to the selected connection circuit side, and therefore, during the period TB, as in the case of FIG. 2, the transistor Q1 (or Q2) is turned on and its state is maintained as information "1", thus writing information "1" into the memory circuit Uii.
又斯る状態より第２図の場合と同様にクロツクパルス源
Ｋより第３図Ａに示す如きクロックパルス列ＣＰを得、
ワード線Ｗｉに第３図Ｂに示す如き制御パルスＷＰｉを
与え、更にビット線Ｂｊ （又はＢ′ｉ）を期間ＴＢと
同じ期間に於て出力回路Ｈ２に接続するものとすれば、
第２図の場合と同様に期間ＴＢに於てビット線Ｂｉ（又
はＢ′ｉ ）が低レベルとなりそしてそれが出力回路Ｈ
２にてメモリ回路Ｕｉｉの「１」の情報の読出しがなさ
れることとなるものである。Also, from this state, as in the case of FIG. 2, a clock pulse train CP as shown in FIG. 3A is obtained from the clock pulse source K,
If we apply a control pulse WPi as shown in FIG. 3B to the word line Wi and further connect the bit line Bj (or B'i) to the output circuit H2 during the same period as the period TB,
As in the case of FIG. 2, during the period TB, the bit line Bi (or B'i) becomes low level and the output circuit H
At step 2, the information "1" in the memory circuit Uii is read out.
勿論第２図の場合と同様に上述せるメモリ回路Ｕｉｉへ
の情報「１」の書込がなされていない場合は、メモリ回
路Ｕｉｊに情報「０」の書込がなされていることを意味
し、又斯る状態より上述せる読出しをなせば出力回路Ｈ
２にてメモリ回路Ｕｉｊの情報が「０」であるとして読
出されるものである。Of course, as in the case of FIG. 2, if the information "1" is not written to the memory circuit Uii described above, it means that the information "0" is written to the memory circuit Uij. In addition, if the above-mentioned reading is performed from such a state, the output circuit H
2, the information in the memory circuit Uij is read as "0".
従って第５図に示す本発明によるメモリ装置に依れば、
第２図に示す従来のメモリ装置と同様のメモリ機能が得
られるものであるが、この場合、そのメモリ回路Ｕｉｉ
のトランジスタＱ１及びＱ２の負荷Ｌ１及びＬ２のトラ
ンジスタＱ１及びＱ２側とは反対側が、ビット線Ｂｉ及
びＢ′の何れかに接続されていて第２図の場合の如くに
電源線Ｆｊを介して電源端子ＶＤに接続されていないの
で、第２図の場合の如くに電源線Ｆｉを要さず、この為
本発明のメモリ装置によれば、それを所謂半導体モノリ
シックに半導体集積化して構成するものとした場合その
構成を第２図の場合に比し高密度、小型化することが出
来る大なる特徴を有するものである。Therefore, according to the memory device according to the present invention shown in FIG.
Although the same memory function as the conventional memory device shown in FIG. 2 can be obtained, in this case, the memory circuit Uii
The sides of the loads L1 and L2 of the transistors Q1 and Q2 opposite to the transistors Q1 and Q2 are connected to either the bit lines Bi or B', and the power is supplied via the power line Fj as in the case of FIG. Since it is not connected to the terminal VD, there is no need for a power supply line Fi as in the case of FIG. In this case, it has a great feature that the structure can be made higher density and smaller than the case shown in FIG.
又上述せる本発明のメモリ装置の場合、メモリ回路Ｕ１
，Ｕ漏・・・・・・・・・ｉＵＭＩ ： Ｕ１２ｔ Ｕ
３２・・・・・・・・・ＵＭ２ ｒ・・・・・・・・・
；ＵＩＮｔＵ３Ｎ・・・・・・・・・ＵＭＮの負荷Ｌ１
及びＬ２のトランジスタＱ１及びＱ２側とは反対側が夫
々ビット線Ｂ’， ， Ｂ；・・・・・・・・・；Ｂ（
に、メモリ回路Ｕ２１，Ｕ４、・・・・・・・・・Ｕ（
Ｍ−ｔ ），： Ｕ２２ ，Ｕ４２・・・・・・・・・
Ｕ（Ｍ−１）２’・・・・・・・・・’ Ｕ２Ｎ ＋
Ｕ４Ｎ・・・・・・・・・Ｕ（Ｍ−ｔ）Ｎの負荷Ｌ１及
びＬ２のトランジスタＱ１及びＱ２側とは反対側がビッ
ト線Ｂ １ ： Ｂ２ ：・・・・・・・・・；ＢＮに
夫々接続されていることにより各ビット線に接続せるメ
モリ回路の数が略々等しいので、各メモリ回路に流れ込
む電流が互に略々等しいものとなり、従って安定なメモ
リ機能が得られるものである。Furthermore, in the case of the memory device of the present invention described above, the memory circuit U1
, U leakage...iUMI: U12t U
32・・・・・・・・・UM2 r・・・・・・・・・
; UINtU3N・・・・・・・・・Load L1 of UMN
The opposite sides of transistors Q1 and Q2 of L2 are connected to bit lines B', , B;
, memory circuits U21, U4, ......U(
M-t),: U22, U42...
U(M-1)2'......' U2N +
The side opposite to the transistors Q1 and Q2 of the loads L1 and L2 of U4N......U(M-t)N is the bit line B1: B2:...;BN Since the number of memory circuits connected to each bit line is approximately equal, the current flowing into each memory circuit is approximately equal to each other, and a stable memory function can therefore be obtained. .
尚上述に於ては本発明の僅かな例を示したに留まり、図
示説明はこれを省略するも例えば第５図にて上述せる構
成に於ける充電用回路ＤＩに於て点線図示の如くトラン
ジスタＱ７及びＱ８と並列にインピーダンス素子Ｘ１及
びＸ２を接続して、メモリ回路Ｕｉ の負荷Ｌ１及びＬ
２のトランジスタＱ１及びＱ２がビット線に接続されて
いることによりメモリ回路Ｕｉ での電流消費に基きビ
ット線Ｂ 及びＢ ′，の電圧レベルが無視し得ないも
のとした場合、それを補償する様にすることも出来、更
にメモリ回路の負荷Ｌ１及びＬ２を第６図に示す如くダ
イオードの如き単方向性素子ＤＬとインピーダンス素子
ＸＬとの直列回路とし、而してその場合の負荷Ｌ１及び
Ｌ２をビット線側よりトランジスタＱ１及びＱ２側に素
子ＤＬを通じて電流が供給される極性を以って接続し、
メモリ回路側よりビット線側への不必要な放電を回避す
る様になすことも出来、勿論メモリ回路に用いられてい
るトランジスタをＰチャンネル型に代え、これに応じて
クロツクパルス列、制御パルス及び書込用パルスの極性
も上述せる場合とは逆とすることも出来、その他本発明
の精神を脱することなしに種種の変更をなし得るであろ
う。The above description has only shown a few examples of the present invention, and illustrations and explanations thereof will be omitted. For example, in FIG. Impedance elements X1 and X2 are connected in parallel with Q7 and Q8 to reduce loads L1 and L of the memory circuit Ui.
If the voltage level of the bit lines B and B' becomes non-negligible due to the current consumption in the memory circuit Ui due to the transistors Q1 and Q2 of the second transistor being connected to the bit line, there is a method to compensate for this. Furthermore, the loads L1 and L2 of the memory circuit can be made into a series circuit of a unidirectional element DL such as a diode and an impedance element XL as shown in FIG. Connected with polarity such that current is supplied from the bit line side to the transistors Q1 and Q2 through the element DL,
It is also possible to avoid unnecessary discharge from the memory circuit side to the bit line side, and of course replace the transistors used in the memory circuit with P-channel types, and adjust the clock pulse train, control pulses, and The polarity of the write pulse may also be reversed from that described above, and various other changes may be made without departing from the spirit of the invention.
第１図及び第２図は夫々従来のメモリ回路及びメモリ装
置を示す接続図、第３図はその説明に供する波形図、第
４図及び第５図は夫々本発明によるメモリ回路及びメモ
リ装置の一例を示す接続図、第６図はそれに用いる負荷
の他の例を示す接続図である。1 and 2 are connection diagrams showing a conventional memory circuit and a memory device, respectively, FIG. 3 is a waveform diagram for explaining the same, and FIGS. 4 and 5 are diagrams of a memory circuit and a memory device according to the present invention, respectively. A connection diagram showing one example, and FIG. 6 is a connection diagram showing another example of a load used therein.
Claims (1)
・・ＵＭと、複数Ｍ本の制御用線Ｗ，，Ｗ，・・・・・
・・・・ｗＭと、第１及び第２の書込・読出用線とを具
備し、上記メモリ回路Ｕ，（ｉ＝１，２・・・・・・・
・・Ｍ）が、ドレインが第１の負荷に、ソースが接地に
夫々接続せる第１のＭＩＳ電界効果型トランジスタと、
ドレインが第２の負荷及び上記第１のＭＩＳ電界効果型
トランジスタのゲートに、ソースが接地に、ゲートが上
記第１のＭＩＳ電界効果型トランジスタのドレインに夫
々接続せる第２のＭＩＳ電界効果型トランジスタと、ド
レイン及びソースの何れか一方が上記第１のＭＩＳ電界
効果型トランジスタのドレイン及び上記第１の負荷の接
続中点に、他方が上記第１の書込・読出用線に、ゲート
が上記制御用線Ｗ，に夫々接続せる第３のＭＩＳ電界効
果型トランジスタと、ドレイン及びソースの何れか一方
が上記第２のＭＩＳ電界効果型トランジスタのドレイン
及び上記第２の負荷の接続中点に、他方が上記第２の書
込・読出用線に、ゲートが上記制御用信号線Ｗｉに夫々
接続せる第４のＭＩＳ電界効果型トランジスタとを具備
するメモリ装置に於いて、上記複数Ｍ個のメモリ回路Ｕ
，，Ｕ２−・・・・・・・ＵＭを２分した場合のその一
方のメモリ回路に関し、その上記第１及び第２の負荷の
上記第１及び第２のＭＩＳ電界効果型トランジスタ側と
は反対側が上記第１の書込・読出用線に、他方のメモリ
回路に関し、その上記第１及び第２の負荷の上記第１及
び第２のＭＩＳ電界効果型トランジスタ側とは反対側が
上記第２の書込・読出用線に夫々共通に接続されてなる
事を特徴とするメモリ装置。1 M plurality of memory circuits U, , U2...
...UM and multiple M control lines W,,W,...
. . wM and first and second write/read lines, and the memory circuit U, (i=1, 2 . . .
...M) is a first MIS field effect transistor whose drain is connected to a first load and whose source is connected to ground, respectively;
a second MIS field effect transistor having a drain connected to a second load and a gate of the first MIS field effect transistor, a source connected to ground, and a gate connected to the drain of the first MIS field effect transistor; , one of the drain and source is connected to the connection midpoint between the drain of the first MIS field effect transistor and the first load, the other is connected to the first write/read line, and the gate is connected to the connection point between the drain and the first load. a third MIS field effect transistor connected to the control line W, and one of its drain and source connected to the connection midpoint of the drain of the second MIS field effect transistor and the second load; In the memory device, the plurality of M memories each include a fourth MIS field effect transistor, the other of which is connected to the second write/read line, and the gate of which is connected to the control signal line Wi, respectively. circuit U
,, U2-... Regarding one of the memory circuits when UM is divided into two, what is the first and second MIS field effect transistor side of the first and second loads? The opposite side is connected to the first write/read line, and the side opposite to the first and second MIS field effect transistor sides of the first and second loads is connected to the second memory circuit. A memory device characterized in that the memory device is commonly connected to write and read lines respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53153366A JPS5813998B2 (en) | 1978-12-11 | 1978-12-11 | memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53153366A JPS5813998B2 (en) | 1978-12-11 | 1978-12-11 | memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5580885A JPS5580885A (en) | 1980-06-18 |
| JPS5813998B2 true JPS5813998B2 (en) | 1983-03-16 |
Family
ID=15560874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53153366A Expired JPS5813998B2 (en) | 1978-12-11 | 1978-12-11 | memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5813998B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4976437A (en) * | 1972-11-24 | 1974-07-23 | ||
| JPS5255336A (en) * | 1975-10-30 | 1977-05-06 | Fairchild Camera Instr Co | Memory cell |
-
1978
- 1978-12-11 JP JP53153366A patent/JPS5813998B2/en not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4976437A (en) * | 1972-11-24 | 1974-07-23 | ||
| JPS5255336A (en) * | 1975-10-30 | 1977-05-06 | Fairchild Camera Instr Co | Memory cell |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5580885A (en) | 1980-06-18 |
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