JPS5580885A - Memory circuit and memory device using the said memory circuit - Google Patents

Memory circuit and memory device using the said memory circuit

Info

Publication number
JPS5580885A
JPS5580885A JP15336678A JP15336678A JPS5580885A JP S5580885 A JPS5580885 A JP S5580885A JP 15336678 A JP15336678 A JP 15336678A JP 15336678 A JP15336678 A JP 15336678A JP S5580885 A JPS5580885 A JP S5580885A
Authority
JP
Japan
Prior art keywords
memory
load
cell
line
fetq5
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15336678A
Other languages
Japanese (ja)
Other versions
JPS5813998B2 (en
Inventor
Nobuaki Ieda
Takeshi Takeya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP53153366A priority Critical patent/JPS5813998B2/en
Publication of JPS5580885A publication Critical patent/JPS5580885A/en
Publication of JPS5813998B2 publication Critical patent/JPS5813998B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To eliminate the power line of the static memory and thus to realize a high density by supplying the power voltage to load FET of the memory cell via the bit line. CONSTITUTION:The opposite side of n-type FETQ5 and Q6 for load L1 and L2 which are connected to middle points P1 and P2 of memory FF formed with n-type FETQ1 and Q2 of memory cell U is connected to bit line B1 among lines B1 and B1'. Then the impedance of load L1 and L2 are selected so that the time constant of the gate capacity of FETQ1 and load L2 may be larger than the clock pulse cycle. Thus the power voltage passing through bit number B' is supplied with no connection of the power line to FETQ5 and Q6 in the fixed cycle period synchronous with the clock pulse. And the reverse current preventing diode or the like is provided between bit line B1' and FETQ5/Q6. As a result, the writing and the reading can be carried out with no effect given to line B1' due to cell U selected by control wire W. Accordingly, if the memory device is formed with the similar cell, the exclusive power line to supply the power voltage to each cell can be omitted to realize a high- density memory device.
JP53153366A 1978-12-11 1978-12-11 memory device Expired JPS5813998B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53153366A JPS5813998B2 (en) 1978-12-11 1978-12-11 memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53153366A JPS5813998B2 (en) 1978-12-11 1978-12-11 memory device

Publications (2)

Publication Number Publication Date
JPS5580885A true JPS5580885A (en) 1980-06-18
JPS5813998B2 JPS5813998B2 (en) 1983-03-16

Family

ID=15560874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53153366A Expired JPS5813998B2 (en) 1978-12-11 1978-12-11 memory device

Country Status (1)

Country Link
JP (1) JPS5813998B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4976437A (en) * 1972-11-24 1974-07-23
JPS5255336A (en) * 1975-10-30 1977-05-06 Fairchild Camera Instr Co Memory cell

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4976437A (en) * 1972-11-24 1974-07-23
JPS5255336A (en) * 1975-10-30 1977-05-06 Fairchild Camera Instr Co Memory cell

Also Published As

Publication number Publication date
JPS5813998B2 (en) 1983-03-16

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