JPS58123744A - Manufacture of lead frame and semiconductor device - Google Patents
Manufacture of lead frame and semiconductor deviceInfo
- Publication number
- JPS58123744A JPS58123744A JP569882A JP569882A JPS58123744A JP S58123744 A JPS58123744 A JP S58123744A JP 569882 A JP569882 A JP 569882A JP 569882 A JP569882 A JP 569882A JP S58123744 A JPS58123744 A JP S58123744A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- plated
- semiconductor chip
- metal
- wire bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は半導体装置のリードフレーム及びそのリードフ
レームを使用した半導体装置の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a lead frame for a semiconductor device and a method for manufacturing a semiconductor device using the lead frame.
（２）技術の背景
半導体装置の製造に関しては例えば図に示すような１）
−ドフレームが使用されている０図面は連続しているリ
ードフレームの一部であって一半導体装置用のリードフ
レームで、外部端子部分で隣の半導体装置用のり−ドフ
レームの外部端子と接続されている。図に於いて１はフ
レーム部分、２は半導体チップ搭載部、３は外部端子部
、３′は隣接する半導体装置の外部端子部、４はモール
ド封止された時に樹脂の中に位置する部分、５はモ−ル
ド樹脂の流れ防止のための連結部分、５′は連結部分に
接続している端子部分、６は半導体チップとワイヤボン
ディングされるワイヤボンディング部である。(2) Technical background Regarding the manufacturing of semiconductor devices, for example, as shown in the figure 1)
-The drawing in which a board frame is used is a part of a continuous lead frame, and is a lead frame for one semiconductor device, and the external terminal part is connected to the external terminal of the adjacent board frame for a semiconductor device. has been done. In the figure, 1 is a frame part, 2 is a semiconductor chip mounting part, 3 is an external terminal part, 3' is an external terminal part of an adjacent semiconductor device, 4 is a part located in the resin when molded and sealed, Reference numeral 5 designates a connecting portion for preventing mold resin from flowing, 5' represents a terminal portion connected to the connecting portion, and 6 represents a wire bonding portion to be wire-bonded to the semiconductor chip.
半導体装量の製造に際しては、半導体チップ搭載部に半
導体チップを熱圧着等で堆付け、半導体チップく形成さ
れたボンディング部分とリードフレームのワイヤボンデ
ィング部６とをアルミニウム或いは金線等で接続し、モ
ールド型内に入れ、樹脂モールドする。この際連結部分
５及び端子部５′の部分で金型がリードフレームと接触
し、この部分でモールドの流れが止められる。モールド
処理後７レーム部分１及び連結部分５は切）離され、且
つ隣接する半導体装置とも切断されて装置は完成する。When manufacturing a semiconductor component, a semiconductor chip is deposited on a semiconductor chip mounting part by thermocompression bonding or the like, and the bonding part formed on the semiconductor chip and the wire bonding part 6 of the lead frame are connected with aluminum or gold wire, etc. Place it in a mold and mold it with resin. At this time, the mold comes into contact with the lead frame at the connecting portion 5 and the terminal portion 5', and the flow of the mold is stopped at this portion. After the molding process, the seven frame portions 1 and the connecting portions 5 are separated, and the adjacent semiconductor devices are also cut to complete the device.
（３） 従来技術と問題点
このようなリードフレームとして要求される条件として
は、半導体チップの接着が容易で、アルミニウム或いは
金線とのワイヤボンディングが確実に行なえることと、
外部端子をプリント板に実その九め従来は鉄ニツケル合
金であるコバールや４２アロイ、鋼合金である１９４ア
ロイのようなリードフレームの基板材料に、金属及び半
導体との接着が良く且つ半田付特性の嵐い例えば金や銀
を全面メッキし九リードフレームが使用されていた０
しかしながら金中銀は高偵な材料であるため、コスト低
減のために１別のリードフレームが提案されている。こ
れは半導体チップ搭載部２及びワイヤボンディング部６
には、金属及び半導体装置との接着のよい金或いは銀メ
ッキ會行ない、端子部分３には、プリント板実装時の半
田付特性のよいスズ或いは半田メッキを行なり九リード
フレームである。(3) Prior art and problems The conditions required for such a lead frame are that semiconductor chips can be easily bonded and wire bonding with aluminum or gold wire can be performed reliably.
External terminals are used on printed circuit boards Conventionally, lead frame substrate materials such as iron-nickel alloy Kovar and 42 alloy, and steel alloy 194 alloy have good adhesion to metals and semiconductors and have good solderability. For example, nine lead frames were used that were entirely plated with gold or silver.However, since gold and silver are expensive materials, other lead frames have been proposed to reduce costs. This is the semiconductor chip mounting part 2 and the wire bonding part 6.
The lead frame is plated with gold or silver for good adhesion to metals and semiconductor devices, and the terminal portion 3 is plated with tin or solder, which has good soldering characteristics when mounted on a printed board.
しかしながらこのリードフレームに於いては連結部分５
及びそれに接−している端子部分５′にはモールドの際
金型が接触し、その部分は１８０℃前後の温度となる丸
め、耐熱性の悪いスズや半田メッキを仁の部分に行なう
ことができなかう九〇このため端子部分５′はメッキ処
理が行なわれず、コバール等の基板が露出した伏線にな
っていた。However, in this lead frame, the connecting portion 5
The terminal portion 5' that is in contact with it is in contact with the mold during molding, and the temperature of that portion is around 180°C, so it is difficult to roll it up and plate the inner portion with tin or solder, which has poor heat resistance. For this reason, the terminal portion 5' was not plated, and the board, such as Kovar, was left exposed.
特にこの端子部分は製品完成時には曲げ加工を施される
ため、この基板の露出部分で腐蝕が起るという欠点を有
していた。In particular, since this terminal portion is bent when the product is completed, it has the disadvantage that corrosion occurs in the exposed portion of the board.
（４）発−の目的
本発明は上記欠点を除去したリードフレーム及び半導体
装置の製造方法を得ることを目的とする。(4) Purpose of the invention The object of the present invention is to provide a lead frame and a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks.
（５）発明の構成
すなわち本発明のリードフレームは基板全面がニッケル
メッキされ、半導体チップ搭載部及びワイヤボンディン
グ部には金属及び半導体との接着性の良い金属のメッキ
が該ニッケル上に施され、モールド処理時の金型接触部
以外の外部端子部にはプリント板実装時の接着を容易に
する金属のメッキが該ニッケルメッキ上に施されている
ことを特徴とする。(5) Structure of the invention, that is, in the lead frame of the present invention, the entire surface of the substrate is plated with nickel, and the semiconductor chip mounting part and the wire bonding part are plated with a metal that has good adhesion to metals and semiconductors, and The external terminal portion other than the mold contact portion during mold processing is characterized in that metal plating is applied on the nickel plating to facilitate adhesion during printed board mounting.
父上配本発明のり−ド７レームのニッケルメッキの厚さ
は０．３〜３μ説であるとよい。The thickness of the nickel plating of the glue board 7 frame of the present invention is preferably 0.3 to 3μ.
更に本発明は上記リードフレームを使用して半導体装置
を製造することも特徴とするものである。Furthermore, the present invention is characterized in that a semiconductor device is manufactured using the above lead frame.
なお上記説明で金属及び半導体との接着性の良い金属と
しては金或いは銀等があり、又プリント板実装時の接着
を容易にする金属としてはスズや半田が好適である。In the above description, metals that have good adhesion to metals and semiconductors include gold, silver, etc., and tin and solder are suitable as metals that facilitate adhesion during printed board mounting.
（６）発明の実施例
ｊｌｌＥ１図によりて本発明の詳細な説明する。まず従
来と同様の材質のリードフレーム基板全面にニッケルメ
ッキを施す。メッキ厚さは０．３〜３Ｊ１１１とする。(6) Embodiment of the Invention The present invention will be explained in detail with reference to FIG. First, nickel plating is applied to the entire surface of the lead frame board, which is made of the same material as before. The plating thickness is 0.3 to 3J111.
ニッケルメッキの厚さが０．３ｓ賜以下の場合には腐蝕
防止の効果が薄くな〕一方３ｊｍ以上になると端子部分
５′の曲げ特性が悪くなシ（メツキクラック等が生ずる
）、本来の腐蝕防止効果がうすれる０次に半導体チップ
搭載部２及びワイヤボンデ４ング部６に金或いは銀メッ
キを行ない外部端子部分３にスズ或いは半田メッキを行
なう〇この場合モールド樹脂の流れ防止のための連結部
分５及びそれに接続している端子部分５′にはスズ或い
は半田メッキは行なわない。これは前述の如くこの部分
にはモールド処理時の金臘が接触し、熱によってメッキ
が変形するのを防ぐためである。If the thickness of the nickel plating is less than 0.3 mm, the corrosion prevention effect will be weak; on the other hand, if it is more than 3 mm, the bending properties of the terminal portion 5' will be poor (metal cracks etc. will occur), and the corrosion will be reduced. The prevention effect is weakened. Next, the semiconductor chip mounting part 2 and the wire bonding part 6 are plated with gold or silver, and the external terminal part 3 is plated with tin or solder. In this case, the connecting part is used to prevent the mold resin from flowing. 5 and the terminal portion 5' connected thereto are not plated with tin or solder. This is to prevent the plating from being deformed by heat due to the contact of the metal plate during the molding process, as described above.
（７）発明の効果
以上のように本発明によれば、リードフレーム全面にニ
ッケルメツ中が施されるために、リードフレームの基板
材料が露出することがなく、従ってこの部分の腐蝕を防
止することができる。(7) Effects of the Invention As described above, according to the present invention, since the nickel metal coating is applied to the entire surface of the lead frame, the substrate material of the lead frame is not exposed, thus preventing corrosion of this part. Can be done.
又ニッケルは比較的安価な金属であるため、全面金や鎖
を施したり−ド７レームに比べて安価なリードフレーム
を得ることができ、このリードフレームを使用すること
によシ、低価格の半導体装置の製造方法を得ることがで
きる。本発明は前処理としてのニッケルメッキが耐腐食
性及び価格面から特に最適であることを見出したもので
ある。In addition, since nickel is a relatively inexpensive metal, it is possible to obtain a lead frame that is less expensive than a lead frame that is coated with gold or a chain on the entire surface, and by using this lead frame. A method for manufacturing a semiconductor device can be obtained. The present invention is based on the discovery that nickel plating as a pretreatment is particularly optimal in terms of corrosion resistance and cost.
なお本発明は第１図に示したり−ド７レームで説明した
が、リードフレームの形状としては、このようなもの以
外にも広く適用することができる。Although the present invention is shown in FIG. 1 and explained in terms of a frame, it can be applied to a wide variety of lead frame shapes other than these.
、４、図面の簡単な説明
図面は本発明を説明するためのり−ド７レームの上面図
である。図に於いて、ｌ杜７レーム部分。4. Brief Description of the Drawings The drawing is a top view of a board 7 frame for explaining the present invention. In the diagram, the 7th frame part.
２は半導体チップ搭載部、３は外部端子部 ３／は封止
された時に樹脂の中に位置する部分、５はモールド樹脂
の流れ防止の丸めの連結部分、５′は連結部分く接続し
ている端子部分、６はワイヤボンディングである。2 is the semiconductor chip mounting part, 3 is the external terminal part, 3/ is the part located in the resin when sealed, 5 is the rounded connecting part to prevent the mold resin from flowing, 5' is the connecting part. The terminal portion 6 is wire bonding.
Claims (3)
載部及びワイヤボンディング部には金属及び半導体との
接層性の良い金属のメッキが該ニッケルメッキ上に施さ
れ、モールド処理時の金型接触部以外の外部端子部には
プリント板実装時の接着を容易にする金属のメッキが該
ニッケルメッキ上に施されていることを特徴とするリー
ドフレーム。(1) The entire surface of the board is nickel plated, and the semiconductor chip mounting area and wire bonding area are plated with a metal that has good contact with metal and semiconductors, and the mold contact area during mold processing is applied. A lead frame characterized in that external terminals other than the nickel plating are plated with metal to facilitate adhesion when mounted on a printed board.
とを特徴とする特許請求の範囲第１項記載のリードフレ
ーム。(2) The lead frame according to claim 1, wherein the thickness of the nickel plating is 0.3 to 34 m.
載部及びワイヤボンディング部には金属及び半導体との
接着性の曳い金属のメッキが腋ニッケルメッキ上に施さ
れモールド処理時の金製接触部以外の外部端子部にはプ
リント板実装時の接着を容易にする金属のメッキが該ニ
ッケルメッキ上に施されているリードフレームの該半導
体チップ搭載部に半導体チップを搭載し、該半導体チッ
プとリードフレームをワイヤボンディングし、その後モ
ールド成形により樹脂封止することを特徴とする半導体
装置の製造方法。(3) The entire surface of the board is nickel-plated, and the semiconductor chip mounting area and wire bonding area are plated with metal that has adhesive properties with metal and semiconductors, and the underarm nickel plating is applied to the areas other than the gold contact areas during molding. A semiconductor chip is mounted on the semiconductor chip mounting part of the lead frame, in which the external terminal part is plated with metal to facilitate adhesion during printed board mounting.The semiconductor chip is mounted on the semiconductor chip mounting part of the lead frame. A method for manufacturing a semiconductor device, comprising wire bonding and then resin sealing by molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP569882A JPS58123744A (en) | 1982-01-18 | 1982-01-18 | Manufacture of lead frame and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP569882A JPS58123744A (en) | 1982-01-18 | 1982-01-18 | Manufacture of lead frame and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58123744A true JPS58123744A (en) | 1983-07-23 |
Family
ID=11618317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP569882A Pending JPS58123744A (en) | 1982-01-18 | 1982-01-18 | Manufacture of lead frame and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58123744A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6139560A (en) * | 1984-07-30 | 1986-02-25 | Hitachi Ltd | Lead attaching method |
| CN105702656A (en) * | 2014-12-10 | 2016-06-22 | 意法半导体私人公司 | Integrated circuit device with plating on lead interconnection point and method of forming the device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51130170A (en) * | 1975-05-07 | 1976-11-12 | Nec Corp | Ic lead frame process |
| JPS5221769A (en) * | 1975-08-11 | 1977-02-18 | Fujitsu Ltd | Mold ic producing system |
-
1982
- 1982-01-18 JP JP569882A patent/JPS58123744A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51130170A (en) * | 1975-05-07 | 1976-11-12 | Nec Corp | Ic lead frame process |
| JPS5221769A (en) * | 1975-08-11 | 1977-02-18 | Fujitsu Ltd | Mold ic producing system |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6139560A (en) * | 1984-07-30 | 1986-02-25 | Hitachi Ltd | Lead attaching method |
| JPH038114B2 (en) * | 1984-07-30 | 1991-02-05 | Hitachi Ltd | |
| CN105702656A (en) * | 2014-12-10 | 2016-06-22 | 意法半导体私人公司 | Integrated circuit device with plating on lead interconnection point and method of forming the device |
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