JPS58115957A - Pulse transmission and reception circuit - Google Patents

Abstract

PURPOSE:To transmits a signal between both ends of a transmission line simultaneously and independently, to reduce the number of transmission lines between function blocks and to attain a small-sized and high speed device, by connecting a pulse transmission/reception circuit consisting of a transmission line drive circuit and two reception circuits to both ends of the transmission line. CONSTITUTION:When an input terminal 36 is high level, since a potential of an output 82 of a decoder circuit 34 is -E and a reference potential VR of the 1st reception circuit 32 is -1/2E, a TR52 is interrupted, the circuit 32 is reception state, and the potential at an output 83 is also -E, but a reference potential VR2 of the 2nd reception circuit 33 is -3/2E, then a TR62 is conductive and the circuit 33 is in reception disable state. With the input terminal 36 at low level, the circuit 32 is in reception disable state and the reception circuit 33 is in reception enable state. That is, when the input terminal 36 is high level, the level of a terminal 37 connected to the transmission line depends on 0 or -E in response to the input state of drive circuits connected to the other end, and the reception is done at the circuit 32, and when the input terminal 36 is low level, the level of the terminal 37 is -E or -2E, and the reception is done by the circuit 33.

Description

【発明の詳細な説明】 〈発明の背−厭〉 この発明は１本の伝送線路によって同時かつ独立の双方
向パル７４６月伝送を町ｎシとするパルス送受イη（ロ
）路に関する。DETAILED DESCRIPTION OF THE INVENTION <Background of the Invention> The present invention relates to a pulse transmission/reception path in which simultaneous and independent two-way pulse transmission is performed by one transmission line.

ディジタル集積回路技術の進歩によって電子計算機を中
心とする情報処３Ｂ！装置の発展には著しいものがある
。これらの情報処理装置内の憎蛇ブロック間におけるパ
ルス信号の伝送ｉｔ、極めて甫資な昧腕となっている。Advances in digital integrated circuit technology have led to information processing 3B centered on electronic computers! The development of equipment has been remarkable. The transmission of pulse signals between the blocks in these information processing devices has become an extremely costly and difficult task.

すなわち、ｍｈｃブロック内におけるテータ処理Ｉｏ回
路は集積回路技術の進歩によって著しく尚密度化、小型
化されてきたが、機能ブロック間においてはその接続に
要する信号線本数のため物理的に小型化が制約されてい
る。このためそれらの機能ブロック…１のパルス伝送に
要する時間によって装置の性能の向上も制約されている
。In other words, the data processing Io circuit within the MHC block has become significantly more dense and compact due to advances in integrated circuit technology, but physical miniaturization is limited by the number of signal lines required for connection between functional blocks. has been done. For this reason, improvement in the performance of the device is also restricted by the time required for pulse transmission of those functional blocks...1.

従来のパルス伝送方式を第１図、第２図に示す一第１図
に示す方式は、各伝送線路１１に対して、その両端に存
在する論理ブロック内の伝送線路駆動回路１２及び伝送
線路受信回路１３が接続され、これらの伝送線路１１に
おいて、同時かつ独立にパルス伝送を行うことができる
。この方式でね伝送すべき信号の数だけ伝送線路１１を
必資とし、これらの？０１．路によって装置の小型化が
妨げられるという欠点がある。The conventional pulse transmission method is shown in FIGS. 1 and 2. The method shown in FIG. A circuit 13 is connected, and pulse transmission can be performed simultaneously and independently on these transmission lines 11. In this method, transmission lines 11 are required as many as the number of signals to be transmitted, and these ? 01. The drawback is that the miniaturization of the device is hindered by the path.

第２図に示す方式は伝送ｉ！１ｊ１ｗｒの数を削減する
ために１本の伝送線路２１の両端にそれぞれ伝送線路駆
動（ロ）路２２及び伝送線路受信回路２３の両者を接続
したものでるる。この細路２１上においては同時かつ独
立にパルス伝送を行うことはできず、時分割によって行
うことが必袂でおる。従ってこの方式においてはディジ
タル信号の伝送に賛する時間が増大し、為性能を要求さ
れる装置においては採用され難いという欠点がある。The system shown in Figure 2 is a transmission i! In order to reduce the number of 1j1wrs, a transmission line driving (b) path 22 and a transmission line receiving circuit 23 are connected to both ends of one transmission line 21, respectively. Pulse transmission cannot be carried out simultaneously and independently on this narrow path 21, and must be carried out by time division. Therefore, this system has the drawback that the time required for transmitting the digital signal increases, and therefore it is difficult to employ it in devices that require high performance.

〈発明の概袂〉 この発明は従来の上記欠点を除去するためになされたも
の′であシ、たソ１本の伝送線路によって同時にしかも
独立に双方向パルス信号伝送を可能、、とし、装置の小
型化及び１８号伝送時間の短縮化を←かることができる
パルス送受信回路を提供することにある。<Summary of the Invention> The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional technology. The object of the present invention is to provide a pulse transmitting/receiving circuit that can reduce the size of the signal and shorten the No. 18 transmission time.

この発明によれば、送信すべきパルス信号を入力とし、
その出力端子が伝送細路に接続される伝送線路駆動回路
と、その伝送線路駆動回路の出力と接続された入力をも
ち、かつそれぞれ異なる基準′両正を有し、前記伝送細
路より受信したパルス信号を再生して出力する第１．第
２の２つの受信回路と、前記伝送線路駆動回路の入力と
接続された入力をもち、その２つの出力の一方が前記第
１の受信回路と接続され、他方の出力が前記第２の受信
回路と接続され、これら２つの出力レベルが論理的に互
いに相補の関係にあり、かつ異なる論理′…゛圧レベル
を有するデコーダ回路と、前記第１、第２の受信回路の
出力とそれぞれ接続された２つの入力とこれら２つの入
力の論理オア出力を弔−するオア回路とを具備しておシ
、１本の伝送線路によって同時かつ独立に双方向パルス
信号の伝送を可能とする。According to this invention, the pulse signal to be transmitted is input,
It has a transmission line drive circuit whose output terminal is connected to the transmission line, and an input connected to the output of the transmission line drive circuit, each having a different standard and positive, and which receives data from the transmission line. The first part reproduces and outputs the pulse signal. It has two second receiving circuits and an input connected to the input of the transmission line driving circuit, one of the two outputs is connected to the first receiving circuit, and the other output is connected to the second receiving circuit. a decoder circuit whose output levels are logically complementary to each other and which have different logical pressure levels; and a decoder circuit which is connected to the outputs of the first and second receiving circuits, respectively. The device is equipped with two inputs and an OR circuit for logically ORing the outputs of these two inputs, making it possible to simultaneously and independently transmit bidirectional pulse signals through one transmission line.

（３） 〈実施例〉 次にこの発明について図面を参照して瞳側に説明する。(3) <Example> Next, this invention will be explained from the pupil side with reference to the drawings.

第３図はこの発明に係わるパルス送受信１路の基本的思
想を表わすブロック図である。図において３０がこの発
明に係わるパルス送受信回路であり、その送受信回路３
０は、１本の伝送線路３９０両端（Ａ端、Ｂ端）にそれ
ぞれ設けられる。パルス送受信回路３０は、端子３６よ
シパルス信号を入力し、端子３７によって出力が伝送線
路３９に接続される伝送線路駆動回路３１と、端子３７
によって伝送−路３９と入力が接続され、伝送線路３９
よシのパルス信号を受信する第１の基準電位を有する第
１の受イぎ回路３２と、同じく端子３７によって伝送線
路３９との入力が接続され、伝送線路３９よシのパルス
信号を受信する第２の基準電位を有する第２の受信回路
３３と、伝送線路脇＃ＩＪＪｕ路３１０入力端子３６と
接収された入力をもち、２つの出力の一方が前記第１の
受４Ｍ回路３２と接続され、他方の出力が前記第２の受
信回路３３（４） と接続され、その２つの出力が論理的に互いに相補の関
係にるり、入力端子３６の一理レベルに応じて前記２つ
の受信回路３２，３３のどちらか一方を有効にして伝送
細路３９よシのパルス信号の受４７４を可能にするため
のデコーダ回路３４と、前記第１．第２の受信回路３２
．３３の出力とそれぞれ接続された２つの入力を有し、
その２つの入力の陶理オアの出力端子３８を有するオア
回路３５とから構成される。FIG. 3 is a block diagram showing the basic idea of one pulse transmitting/receiving path according to the present invention. In the figure, numeral 30 indicates a pulse transmitting/receiving circuit according to the present invention, and the transmitting/receiving circuit 3
0 is provided at both ends (A end, B end) of one transmission line 390, respectively. The pulse transmitting/receiving circuit 30 includes a transmission line drive circuit 31 which receives a pulse signal through a terminal 36 and whose output is connected to a transmission line 39 through a terminal 37;
The transmission line 39 and the input are connected by the transmission line 39.
A first receiving circuit 32 having a first reference potential that receives a pulse signal from the other side is connected to an input to a transmission line 39 through a terminal 37, and receives a pulse signal from the transmission line 39. It has a second receiving circuit 33 having a second reference potential, an input that is connected to the transmission line side #IJJu path 310 input terminal 36, and one of its two outputs is connected to the first receiving 4M circuit 32. , the other output is connected to the second receiving circuit 33 (4), and the two outputs are logically complementary to each other. , 33 to enable reception 474 of a pulse signal through the transmission path 39; Second receiving circuit 32
．． It has 33 outputs and 2 inputs connected respectively,
It is composed of an OR circuit 35 having an output terminal 38 for the two inputs.

〈実施例の具体例〉 第４図はパルス送受信回路３０の具体例を示し、点線で
囲んだ部分Ｕ第３図の伝送線路駆動回路３１、第１の受
信回路３２、第２の受信回路・３３、デコーダ回路３４
、そしてオア回Ｗ１１３５に相当するものであシ、同じ
参照番号を付している。図は回路形式として電流切換型
回路を使った例である。伝送線路駆動回路３１１ｊ：、
トランジスタ４１，４２゜４３と定電流源（ロ）路４４
と抵抗４５．４６とから構成され、レベルシフト回路と
して働くトランジスタ４１０ベースが入力端子３６と接
続され、トランジスタ４３のコレクタと抵抗４６の共通
接続点４７が出力として端子３７と接続され、トランジ
スタ４３のベースには通常入力端子３６のＨＩＧＨ（ｉ
％！ｉｌ）、ＬＯＷ（低）の随理レベルの中間電位から
さらにトランジスタ４１のＶＲＩ分だけ低い電位が基準
電位Ｖａとして与えられる。<Specific Example of Embodiment> FIG. 4 shows a specific example of the pulse transmitting/receiving circuit 30, and the portion U surrounded by the dotted line includes the transmission line drive circuit 31, the first receiving circuit 32, the second receiving circuit, and 33, decoder circuit 34
, and corresponds to OR time W1135, and are given the same reference numbers. The figure shows an example using a current switching type circuit as the circuit type. Transmission line drive circuit 311j:,
Transistors 41, 42゜43 and constant current source (b) path 44
The base of the transistor 410, which functions as a level shift circuit, is connected to the input terminal 36, and the common connection point 47 between the collector of the transistor 43 and the resistor 46 is connected to the terminal 37 as an output. The base normally has the input terminal 36 HIGH (i
%! il), a potential that is further lower by the VRI of the transistor 41 than the intermediate potential of the LOW (low) arbitrary level is given as the reference potential Va.

伝送線路３９の両端（Ａ端、Ｂ端）にそれぞれ接続され
た伝送線路駆動回路３１の入力３６がＡ端、Ｂ端共にＨ
ＩＧＨ（高）のとき鉱、伝送線路３９の電位は０、どち
らか一方がＨＩＧＨで他方がＬＯＷのとき−ＥＸＡ端、
Ｂ端共にＬＯＷのとき一２Ｅとなるように抵抗４６の値
と定電流源４４の電流値が設定されると共に、抵抗４６
は伝送線路３９の終端抵抗としても働くようにその抵抗
値は、伝送線路３９の特性インピーダンスに近い値に設
定される。The input 36 of the transmission line drive circuit 31 connected to both ends (A end, B end) of the transmission line 39 is set to H at both A end and B end.
When it is IGH (high), the potential of the transmission line 39 is 0, and when either one is HIGH and the other is LOW, -EXA terminal,
The value of the resistor 46 and the current value of the constant current source 44 are set so that when both B terminals are LOW, the value of the resistor 46 and the current value of the constant current source 44 are set.
Its resistance value is set to a value close to the characteristic impedance of the transmission line 39 so that it also functions as a terminating resistance of the transmission line 39.

第１の受信囲路３２はトランジスタ５１，５２．５３と
定電流源回路５４と抵抗５５とから成る２人カアンドグ
ートと、定電流源５６と抵抗５７、コンデンサ５８とか
ら成る前記２人カアンドゲートに与えるべき第１の基準
電位発生回路とによっテ構成される。トランジスタ５３
のベースに与えられる第１の基準電位Ｖルｌは一７ｉＥ
となるように設定され、コンデンサ５８はＶＲＩの安定
性をはかるだめのものである。The first receiving circuit 32 includes a two-person circuit consisting of transistors 51, 52, 53, a constant current source circuit 54, and a resistor 55, and a two-person circuit consisting of a constant current source 56, a resistor 57, and a capacitor 58. and a first reference potential generation circuit to be applied to. transistor 53
The first reference potential Vl applied to the base of is -7iE
The capacitor 58 is used to measure the stability of the VRI.

第２の受信回路３３は、第１の受信回路３２と同じであ
るが、トランジスタ６３０ベースに与えるべき基準電位
■■が一−Ｅとなるように設定されていることと、この
例では第１．第２の受信回路３２．３３の出力同志を接
続してワイヤドオアとしているためトランジスタ６３の
コレクタ抵抗がないことだけが異なる。The second receiving circuit 33 is the same as the first receiving circuit 32, except that the reference potential to be applied to the base of the transistor 630 is set to be -E, and in this example, the first receiving circuit 33 is ．． The only difference is that the outputs of the second receiving circuits 32 and 33 are connected to form a wired OR, so that the collector resistance of the transistor 63 is not present.

デコーダ回路３４は、トランジスタ７１と抵抗７２から
成る入カニミッタフォロワ回路と、トランジスタ７３．
７４、定電流源回路７５、抵抗７６から成るインバータ
回路と、トランジスタ７７゜７８、定電流源回路７９、
抵抗８０．８１からなるレベルシフト回路とから楢成さ
れる。前記インバータ回路の出力８２は、第１の受信回
路３２の入力トランジスタ５２のベースと接続され、Ｈ
ＩＧＨ（７） レベルがＯ，ＬＯＷレベルが−Ｅとなるように、抵抗７
６の値と定電流源７５の電流値が設定される。前記レベ
ルシフト回路の出力８３は、第２ｃ受信回路３３０入カ
ドランジスタロ２０ペースと接続され、）（ＩＧＨレベ
ルが−Ｅ、ＬＯＷレベルか一２Ｅとなるように抵抗８０
．８１の値と定電流源７９の電流値が設定される。The decoder circuit 34 includes an input limiter follower circuit consisting of a transistor 71 and a resistor 72, and a transistor 73 .
74, an inverter circuit consisting of a constant current source circuit 75, a resistor 76, a transistor 77° 78, a constant current source circuit 79,
It is composed of a level shift circuit consisting of resistors 80 and 81. The output 82 of the inverter circuit is connected to the base of the input transistor 52 of the first receiving circuit 32, and is connected to the base of the input transistor 52 of the first receiving circuit 32.
IGH (7) Connect resistor 7 so that the level is O and the LOW level is -E.
6 and the current value of the constant current source 75 are set. The output 83 of the level shift circuit is connected to the second c receiving circuit 330 input quadrant transistor 20 pace, and the resistor 80 is connected so that the IGH level is -E, LOW level or -2E.
．． 81 and the current value of the constant current source 79 are set.

〈動作説明〉 入力端子３６が）（ＩＧ）Ｉのときは、デコーダ回路３
４の出力８２の電位は−Ｅであシ、第１の受信回路３２
の基準電位Ｖルが−ＴＥであるためトランジスタ５２は
遮断状態で第１の受信回路３２は受信態勢にあり、デコ
ーダ回路３４の出力８３の電位はやはシーＥであるが、
第２の受信回路３３の基準電位Ｖａｎが−ｙＢであるた
めトランジスタ６２は導通状態にあシ、第２の受信回路
３３は受信不可の状態にある。<Operation explanation> When the input terminal 36 is )(IG)I, the decoder circuit 3
4, the potential of the output 82 is -E, and the first receiving circuit 32
Since the reference potential V is -TE, the transistor 52 is cut off and the first receiving circuit 32 is in reception mode, and the potential of the output 83 of the decoder circuit 34 is still CE.
Since the reference potential Van of the second receiving circuit 33 is -yB, the transistor 62 is in a conductive state and the second receiving circuit 33 is in a state in which reception is not possible.

一方、入力端子３６がＬＯＷのときは、デコーダ回路３
４の出力８２の電位はＯであシ、トランジスタ５２鉱導
通状態のため、第１の受信回路３２（８） は受信不可の状態にあり、デコーダ回路３４の出力８３
の電位は一２Ｅであるため、トランジスタ６２が遮断状
態にあシ、□受信回路３３１ｊ受信可の状態にある。On the other hand, when the input terminal 36 is LOW, the decoder circuit 3
The potential of the output 82 of the decoder circuit 34 is O, and the transistor 52 is in a conductive state, so the first receiving circuit 32 (8) is in a state where it cannot receive data.
Since the potential of is -2E, the transistor 62 is in a cut-off state, and the receiving circuit 331j is in a receiving enabled state.

即ち、入力端子３６がＨＩＧＨのときは、伝送線路３９
の一端と接続された端子３７のレベルは、伝送線路３９
の他端に接続された駆動回路の入力状態に応じて０か−
Ｅであシ、この時第１の受信回路３２によって他端から
のパルス信号を受信し、入力端子３６がＬＯＷのときは
、端子３７のレベルは他端の駆動回路の入力状態に応じ
て−Ｅか一２Ｅであシ、この時第２の受信回路３３によ
って他端からのパルス信号を受信する。That is, when the input terminal 36 is HIGH, the transmission line 39
The level of the terminal 37 connected to one end of the transmission line 39 is
0 or - depending on the input state of the drive circuit connected to the other end
If E is selected, the first receiving circuit 32 receives a pulse signal from the other end, and when the input terminal 36 is LOW, the level of the terminal 37 becomes - depending on the input state of the drive circuit at the other end. If it is E or 2E, then the second receiving circuit 33 receives the pulse signal from the other end.

〈変形例〉 オア回路３５は、この例では前述のように、２つの受信
回路３２．３３の出力同志を接続してワイヤドオアとし
ているため単なるバッフて回路となっているが、第８図
に示すようなワイヤドオアだけでもよいし、又通常のゲ
ート回路によるオア回路であってもよいことはもちろん
である。<Modification> As described above, in this example, the OR circuit 35 is a simple buffer circuit because the outputs of the two receiving circuits 32 and 33 are connected to form a wired OR circuit, as shown in FIG. Of course, it is possible to use only a wired OR circuit such as the one described above, or an OR circuit using a normal gate circuit.

デコーダ回路３４の入力は伝送線路駆動回路３１の入力
と直接接続する場合に限らず、第７図に示すように伝送
線路駆動回路３１０レベルシフト用のエミッタフォロワ
回路の出力をデコーダ回路３４の入力と接続しても論理
的には全く同じである。The input of the decoder circuit 34 is not limited to the case where it is directly connected to the input of the transmission line drive circuit 31. As shown in FIG. Even if they are connected, they are logically the same.

伝送線路３９の両端をＡ、Ｂとした時、前述の動作の関
係を示すと第５図に示した表のようになる。この表から
明らかなようにＢ端の伝送線路駆動回路の入力レベルは
、Ａ端における伝送線路脇＃回路の入力レベルとは無関
係にＡ端における受信回路とオア回路とにおいて再生さ
れている。同様にＡ端における伝送線路駆動回路の入力
レベルはＢ端の伝送線路駆動回路の入力レベルと無関係
にＢ端における受信回路とオア回路の出力として得られ
ることは明らかである。When both ends of the transmission line 39 are designated as A and B, the relationship between the above-mentioned operations is shown in the table shown in FIG. 5. As is clear from this table, the input level of the transmission line drive circuit at the B end is reproduced in the receiving circuit and OR circuit at the A end, regardless of the input level of the # circuit beside the transmission line at the A end. Similarly, it is clear that the input level of the transmission line drive circuit at the A end is obtained as the output of the receiving circuit and OR circuit at the B end, regardless of the input level of the transmission line drive circuit at the B end.

第６図はパルス波形を用いてこれらの関係を示したもの
である。FIG. 6 shows these relationships using pulse waveforms.

１　　　　以上は伝送線路３９の電位０．−Ｅ、−２Ｅ
の３つのレベルを識別するのに、基準電位として−１Ｅ
　、−３ｇなる電位を使用したが、これに限定２ する意図はなく、上記伝送線路３９の電位を識別し得る
袖″１位であれば他の基準電位を用いてもよい。1 or more, the potential of the transmission line 39 is 0. -E, -2E
-1E as the reference potential to identify the three levels of
, -3g are used; however, there is no intention to limit the reference potential to this, and other reference potentials may be used as long as the potential of the transmission line 39 can be identified.

又この発明は説明した実施例によってのみ前記した％許
趙求の範囲を限定するものでないことは勿崗である。Also, it goes without saying that the present invention is not intended to limit the scope of the above-mentioned percentages only by the described embodiments.

この発明は以上説明したように、主として伝送線路駆動
回路と２個の受信回路よシ成るパルス送受信回路を１本
の伝送線路の両端Ａ、Ｂに接続することにより、Ａ端よ
ｊＤＢ端へのパルス信号伝送及びＢ端よシＡ端へのパル
ス信号伝送を同時かつ独立に実行することができ、機能
ブロック間において必狭とされる伝送線路本数を削減す
る効果があると共に装置の小型化、高速化を達成するこ
とができる。As explained above, this invention connects a pulse transmitting/receiving circuit mainly consisting of a transmission line driving circuit and two receiving circuits to both ends A and B of one transmission line, thereby transmitting signals from the A end to the jDB end. Pulse signal transmission and pulse signal transmission from the B end to the A end can be performed simultaneously and independently, which has the effect of reducing the number of transmission lines required between functional blocks, and also reduces the size of the device. High speed can be achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図はそれぞれ従来のパルス伝送方式を示す
ブロック図、第３図はこの発明によるパルス送受信回路
を用いたパルス伝送方式を示すブロック図、第４図はこ
の発明によるパルス送受信回路の具体例を示す接続図、
第５図は伝送線路の両端Ａ、Ｈにおけるパルス送受信回
路の各点のレベルの関係を示す図、第６図はパルス波形
による動作説明図、第７図は第４図における伝送線路駆
動回路３１とデコーダ回路３４の他の例を示す図、第８
図は同じく第４図におけるオア回路３５をワイヤドオア
回路のみとした他の例を示す図である。 ３１：伝送線路駆動回路、３２：第１の受信回路、３３
：第２の受信回路、３４：デコーダ（ロ）路、３５：オ
ア回路、３６二人力端子、３７：伝送路接続端子、３８
：出力端子、３９：伝送線路。 特許出願人　　日本電気株式会社 代理人　単針　卓 ７８　図 １１ Ｌ　　　　　ｗ 丁 ５ ３３９−1 and 2 are block diagrams showing a conventional pulse transmission method, FIG. 3 is a block diagram showing a pulse transmission method using a pulse transmission/reception circuit according to the present invention, and FIG. 4 is a pulse transmission/reception circuit according to the present invention. A connection diagram showing a specific example of
FIG. 5 is a diagram showing the level relationship of each point of the pulse transmitting/receiving circuit at both ends A and H of the transmission line, FIG. 6 is an operation explanatory diagram using pulse waveforms, and FIG. 7 is the transmission line drive circuit 31 in FIG. 4. FIG. 8 shows another example of the decoder circuit 34.
This figure is a diagram showing another example in which the OR circuit 35 in FIG. 4 is replaced with only a wired OR circuit. 31: Transmission line drive circuit, 32: First receiving circuit, 33
: Second receiving circuit, 34: Decoder (b) path, 35: OR circuit, 36 Two-power terminal, 37: Transmission line connection terminal, 38
: Output terminal, 39: Transmission line. Patent Applicant NEC Corporation Agent Single Needle Table 78 Figure 11 L w D5 339-

Claims (1)

【特許請求の範囲】[Claims] （１）送信すべきパルス信号を入力とし、出力端子が伝
送線路に接続される伝送線路駆動回路と、その伝送線路
駆動回路の出力と接続された入力をもち、かつそれぞれ
異なる基準電圧を有し、前記伝送線路より受信したパル
ス信号を再生して出力する第１．第２の２つの受信回路
と、前記伝送線路駆動回路の入力と接続された入力をも
ち、２つの出力の一方が前記第１の受信回路と接続され
、他方の出力が前記第２の受信回路と接続され、その２
つの出力レベルが綱理的に互いに相補の関係にあり、か
つ異なるＷ４理電圧レベルを有するデコーダ回路と、前
記第１．第２の受信回路の出力とそれぞれ接続された２
つの入力とこれら２つの入力の制Ｎオア出力を有するオ
ア回路とを具備しておシ、１本の伝送線路によって同時
かつ独立に双方向パルス信号の伝送を可能とするパルス
送受信（ロ）路。(1) A transmission line drive circuit whose input is the pulse signal to be transmitted and whose output terminal is connected to the transmission line, and an input connected to the output of the transmission line drive circuit, each having a different reference voltage. , a first regenerating and outputting the pulse signal received from the transmission line. It has two second receiving circuits and an input connected to the input of the transmission line driving circuit, one of the two outputs is connected to the first receiving circuit, and the other output is connected to the second receiving circuit. is connected, part 2
a decoder circuit whose output levels are theoretically complementary to each other and have different W4 logical voltage levels; 2 connected respectively to the output of the second receiving circuit.
A pulse transmitting/receiving path (b) which is equipped with two inputs and an OR circuit having a control NOR output of these two inputs, and which enables bidirectional pulse signals to be transmitted simultaneously and independently through one transmission line. .