JPS5796541A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5796541A
JPS5796541A JP17299980A JP17299980A JPS5796541A JP S5796541 A JPS5796541 A JP S5796541A JP 17299980 A JP17299980 A JP 17299980A JP 17299980 A JP17299980 A JP 17299980A JP S5796541 A JPS5796541 A JP S5796541A
Authority
JP
Japan
Prior art keywords
film
pad
providing
psg
field insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17299980A
Other languages
Japanese (ja)
Inventor
Tatsuo Yoshino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP17299980A priority Critical patent/JPS5796541A/en
Publication of JPS5796541A publication Critical patent/JPS5796541A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve moisture resistance by providing a PSG film in the vicinity of a bonding pad provided on a field insulating film so as not to allow them to contact each other and by providing an insulating protective film between said PSG film and field insulating film and by providing said film in the manner that said protective film covers the periphery of said pad. CONSTITUTION:An Al bonding pad 4 is provided on a semiconductor substrate 1 having a high concentration impurity region 11 via a field insulating film 2, and a PSG film 3 is provided near said pad. And, an insulating protective film 5 is provided between said pad 4 and film 3, and is made such that said film 5 creeps around said pad 4. Consequently, even if cracks due to a mechanical impact caused by a bonding tool and the like are produced, reduction in moisture resistance can be prevented.
JP17299980A 1980-12-08 1980-12-08 Semiconductor device Pending JPS5796541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17299980A JPS5796541A (en) 1980-12-08 1980-12-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17299980A JPS5796541A (en) 1980-12-08 1980-12-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5796541A true JPS5796541A (en) 1982-06-15

Family

ID=15952302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17299980A Pending JPS5796541A (en) 1980-12-08 1980-12-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5796541A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51123073A (en) * 1975-04-21 1976-10-27 Hitachi Ltd Insulated gate (type) semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51123073A (en) * 1975-04-21 1976-10-27 Hitachi Ltd Insulated gate (type) semiconductor device

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