JPS5787145A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5787145A
JPS5787145A JP55163567A JP16356780A JPS5787145A JP S5787145 A JPS5787145 A JP S5787145A JP 55163567 A JP55163567 A JP 55163567A JP 16356780 A JP16356780 A JP 16356780A JP S5787145 A JPS5787145 A JP S5787145A
Authority
JP
Japan
Prior art keywords
wiring
electrode
pad
region
integration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55163567A
Other languages
Japanese (ja)
Inventor
Hiroyoshi Ohira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP55163567A priority Critical patent/JPS5787145A/en
Publication of JPS5787145A publication Critical patent/JPS5787145A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the chip size as well as to improve the degree of integration for the subject semiconductor device by a method wherein, on the IC substrate of multilayer structure provided with interlayer insulating films, a bonding pad section is formed in an active element region using the wiring metal of the upper layer. CONSTITUTION:In the case of MOSIC, for example, on the gate metal 9 consisting of a polycrystalline Si and the like and a source and drain region 6, an electrode 9 to be connected to the above is formed, and then an interlayer insulating film 10 is formed using a PSG film, polyimide resin and the like, for example. On this interlayer film 10, the wiring metal layer, which will be connected to the electrode wiring 9 on the lower layer, is formed using an Al and the like, and at the same time, a pad 11 to be used for external connection is arranged on the region where FET will be formed. Also, as occasion demands, a bump electrode 13 is provided on the pad 11. Through these procedures, an element region can be arranged as far as to the circumferential section on the chip surface, the chip size can be reduced and the wiring part can also be reduced, thereby enabling to increase the degree of integration.
JP55163567A 1980-11-20 1980-11-20 Semiconductor device Pending JPS5787145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55163567A JPS5787145A (en) 1980-11-20 1980-11-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55163567A JPS5787145A (en) 1980-11-20 1980-11-20 Semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP63285062A Division JPH0214527A (en) 1988-11-11 1988-11-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5787145A true JPS5787145A (en) 1982-05-31

Family

ID=15776355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55163567A Pending JPS5787145A (en) 1980-11-20 1980-11-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5787145A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943536A (en) * 1982-09-03 1984-03-10 Fujitsu Ltd Semiconductor device
JPS6461057A (en) * 1987-09-01 1989-03-08 Fujitsu Ltd Semiconductor device
JPH0193136A (en) * 1987-10-05 1989-04-12 Nec Corp Semiconductor device
JPH0195539A (en) * 1987-10-07 1989-04-13 Toshiba Corp Semiconductor device
JPH02121333A (en) * 1988-10-31 1990-05-09 Toshiba Corp Semiconductor device and its manufacture
JPH03254137A (en) * 1990-03-05 1991-11-13 Toshiba Corp Semiconductor integrated circuit device
US6441467B2 (en) 1997-04-24 2002-08-27 Sharp Kabushiki Kaisha Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film
JP2006024853A (en) * 2004-07-09 2006-01-26 Matsushita Electric Ind Co Ltd Semiconductor device, manufacturing method thereof, and electric characteristic control method thereof
US7326958B2 (en) 2005-04-26 2008-02-05 Matsushita Electric Industrial Co., Ltd. Solid state imaging device
US7573256B2 (en) 2005-07-25 2009-08-11 Seiko Epson Corporation Semiconductor wafer examination method and semiconductor chip manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50141975A (en) * 1974-05-01 1975-11-15
JPS543467A (en) * 1977-06-09 1979-01-11 Nec Corp Semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50141975A (en) * 1974-05-01 1975-11-15
JPS543467A (en) * 1977-06-09 1979-01-11 Nec Corp Semiconductor integrated circuit

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943536A (en) * 1982-09-03 1984-03-10 Fujitsu Ltd Semiconductor device
JPS6461057A (en) * 1987-09-01 1989-03-08 Fujitsu Ltd Semiconductor device
JPH0193136A (en) * 1987-10-05 1989-04-12 Nec Corp Semiconductor device
JPH0195539A (en) * 1987-10-07 1989-04-13 Toshiba Corp Semiconductor device
JPH02121333A (en) * 1988-10-31 1990-05-09 Toshiba Corp Semiconductor device and its manufacture
JPH03254137A (en) * 1990-03-05 1991-11-13 Toshiba Corp Semiconductor integrated circuit device
US6441467B2 (en) 1997-04-24 2002-08-27 Sharp Kabushiki Kaisha Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film
US6650002B1 (en) 1997-04-24 2003-11-18 Sharp Kabushiki Kaishi Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film
US6864562B1 (en) 1997-04-24 2005-03-08 Sharp Kabushiki Kaisha Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film
JP2006024853A (en) * 2004-07-09 2006-01-26 Matsushita Electric Ind Co Ltd Semiconductor device, manufacturing method thereof, and electric characteristic control method thereof
US7326958B2 (en) 2005-04-26 2008-02-05 Matsushita Electric Industrial Co., Ltd. Solid state imaging device
US7573256B2 (en) 2005-07-25 2009-08-11 Seiko Epson Corporation Semiconductor wafer examination method and semiconductor chip manufacturing method
US7598730B2 (en) 2005-07-25 2009-10-06 Seiko Epson Corporation Semiconductor wafer examination method and semiconductor chip manufacturing method

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