JPS576493A - Dynamic memory refreshing circuit - Google Patents

Dynamic memory refreshing circuit

Info

Publication number
JPS576493A
JPS576493A JP8063080A JP8063080A JPS576493A JP S576493 A JPS576493 A JP S576493A JP 8063080 A JP8063080 A JP 8063080A JP 8063080 A JP8063080 A JP 8063080A JP S576493 A JPS576493 A JP S576493A
Authority
JP
Japan
Prior art keywords
signal
timing
dynamic memory
ras
refresh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8063080A
Other languages
Japanese (ja)
Inventor
Akira Naito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8063080A priority Critical patent/JPS576493A/en
Publication of JPS576493A publication Critical patent/JPS576493A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To raise a system margin, by delaying an RAS timing drive signal at the time of refresh, to the point of time of a CAS timing drive signal, through a gate circuit. CONSTITUTION:Unless a refresh busy signal is outputted, an RAS timing drive signal 71 from a timing generator 7 is inputted to a dynamic memory 1 through gates 72, 74, and a CAS timing signal 81 is inputted to the memory 1 through a gate 8. The RAS signal and the CAS signal are stopped by the gates 72, 8, respectively, in accordance with a signal from a refresh busy circuit 5, but the RAS signal is provided to the dynamic memory 1 through gates 73, 74, and timing of refresh is is decided. Since an address set-up time can be taken enough, a system margin is raised.
JP8063080A 1980-06-13 1980-06-13 Dynamic memory refreshing circuit Pending JPS576493A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8063080A JPS576493A (en) 1980-06-13 1980-06-13 Dynamic memory refreshing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8063080A JPS576493A (en) 1980-06-13 1980-06-13 Dynamic memory refreshing circuit

Publications (1)

Publication Number Publication Date
JPS576493A true JPS576493A (en) 1982-01-13

Family

ID=13723669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8063080A Pending JPS576493A (en) 1980-06-13 1980-06-13 Dynamic memory refreshing circuit

Country Status (1)

Country Link
JP (1) JPS576493A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01240614A (en) * 1988-03-19 1989-09-26 Nippon Steel Corp Method for preventing decarbonization of steel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01240614A (en) * 1988-03-19 1989-09-26 Nippon Steel Corp Method for preventing decarbonization of steel

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