JPS5760447A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPS5760447A JPS5760447A JP55136274A JP13627480A JPS5760447A JP S5760447 A JPS5760447 A JP S5760447A JP 55136274 A JP55136274 A JP 55136274A JP 13627480 A JP13627480 A JP 13627480A JP S5760447 A JPS5760447 A JP S5760447A
- Authority
- JP
- Japan
- Prior art keywords
- test
- outputted
- memory
- port
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Microcomputers (AREA)
Abstract
PURPOSE:To prevent an increase of a memory of a testing device, and also to shorten the time required for a test, by simultaneously outputting the data corresponding t plural addresses of a program memory, in a single chip microcomputer. CONSTITUTION:When a microcomputer is executing its real operation, a test signal TEST becomes a low level, an ROM data is outputted to a bus line BUS, and is latched by a port PA. On the other hand, in case the ROM is tested, the test signal TEST becomes a high level, and ROM data DATA1, DATA2 having a 2 address portion are outputted to the bus line BUS. On the other hand, since a clock TA is provided to the port PA, the DATA1 is outputted. Also, since a clock TB is provided to a port PB, the DATA2 is outputted. The test is finished by half of the test time and half of the memory capacity, by detecting the coincidence with the timing of a sampling clock to a memory of a testing device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55136274A JPS5760447A (en) | 1980-09-30 | 1980-09-30 | Integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55136274A JPS5760447A (en) | 1980-09-30 | 1980-09-30 | Integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5760447A true JPS5760447A (en) | 1982-04-12 |
JPS6116099B2 JPS6116099B2 (en) | 1986-04-28 |
Family
ID=15171355
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55136274A Granted JPS5760447A (en) | 1980-09-30 | 1980-09-30 | Integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5760447A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62150441A (en) * | 1985-12-23 | 1987-07-04 | Nec Corp | Single chip microcomputer |
-
1980
- 1980-09-30 JP JP55136274A patent/JPS5760447A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62150441A (en) * | 1985-12-23 | 1987-07-04 | Nec Corp | Single chip microcomputer |
Also Published As
Publication number | Publication date |
---|---|
JPS6116099B2 (en) | 1986-04-28 |
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