JPS5759353A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5759353A
JPS5759353A JP13370980A JP13370980A JPS5759353A JP S5759353 A JPS5759353 A JP S5759353A JP 13370980 A JP13370980 A JP 13370980A JP 13370980 A JP13370980 A JP 13370980A JP S5759353 A JPS5759353 A JP S5759353A
Authority
JP
Japan
Prior art keywords
wiring
shaped
impurities
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13370980A
Other languages
Japanese (ja)
Inventor
Kei Kirita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13370980A priority Critical patent/JPS5759353A/en
Publication of JPS5759353A publication Critical patent/JPS5759353A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To increase the speed of the circuit operation of the semiconductor device and integrate the operation to a high degree by lowering the electric resistance of the wiring of a semiconductor such as Si to which impurities are doped in the semiconductor device using the semiconductor as a wiring material. CONSTITUTION:An insulating film is formed onto a semiconductor substrate 11 in Si, etc., openings are shaped and diffusion regions 12a, 12b, etc. are molded periodic unevenness is formed onto the insulating film 13a of a region, in which wiring must be shaped, through photo-etching, etc., and nuclei for artificial crystal growth are formed. When a non-single crystal silicon film in polycrystal silicon, etc. is shaped on these whole surfaces, impurities are diffused and changed into conductive forms, and energy rays having high density such as laser rays are irradiated to a position where wiring must be formed, impurities are activated electrically while the wiring 15a turned into a single crystal is shaped, and the electric resistance of the wiring is one half or lower of that of electrodes 15b consisting of polycrystals. A wiring pattern is etched, and coated with an insulating laer 16.
JP13370980A 1980-09-27 1980-09-27 Manufacture of semiconductor device Pending JPS5759353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13370980A JPS5759353A (en) 1980-09-27 1980-09-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13370980A JPS5759353A (en) 1980-09-27 1980-09-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5759353A true JPS5759353A (en) 1982-04-09

Family

ID=15111052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13370980A Pending JPS5759353A (en) 1980-09-27 1980-09-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5759353A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4958307A (en) * 1987-11-20 1990-09-18 Kabushiki Kaisha Toshiba Roll mark inspection apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4958307A (en) * 1987-11-20 1990-09-18 Kabushiki Kaisha Toshiba Roll mark inspection apparatus

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