JPS567467A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS567467A
JPS567467A JP8358679A JP8358679A JPS567467A JP S567467 A JPS567467 A JP S567467A JP 8358679 A JP8358679 A JP 8358679A JP 8358679 A JP8358679 A JP 8358679A JP S567467 A JPS567467 A JP S567467A
Authority
JP
Japan
Prior art keywords
film
polycrystal
type
regions
fuse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8358679A
Other languages
Japanese (ja)
Inventor
Norio Kususe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8358679A priority Critical patent/JPS567467A/en
Publication of JPS567467A publication Critical patent/JPS567467A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To facilitate the manufacture of a fuse type PROM semiconductor device having a high integration degree and a high function by growing a polycrystal Si film in a gaseous phase on a semiconductor substrate, selectively oxidizing them and using as semifixed memory elements the polycrystal Si films in regions surrounded by the above polycrystal Si films. CONSTITUTION:On an N-type Si substrate 101 there are provided insulating films 104 made of SiO2, Si3N4 or the like, having predetermined openings 105 and 106. One 105 of the openings is covered with a photoresist film 107, and a P-type base region 106 is diffused and formed in the other opening 106. Then, the film 107 is removed, and a polycrystal Si film 108 is caused to grow in a gaseous phase on the full surface. An Si3N4 film 109 is provided only on the fuse resisting part and electrode wiring path forming region, and is subjected to heat treatment thereby to convert the exposed part of the film 108 into an SiO2 film 114. Thus, polycrystal Si regions 113, 110, 111 and 112 made of a fuse resisting part and an electrode wiring path remain in regions encircled by the film 114, and a film 109 is alternately removed to diffuse P-type and N-type impurities to render the resistance values of these regions at desired ones.
JP8358679A 1979-07-02 1979-07-02 Semiconductor memory device Pending JPS567467A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8358679A JPS567467A (en) 1979-07-02 1979-07-02 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8358679A JPS567467A (en) 1979-07-02 1979-07-02 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS567467A true JPS567467A (en) 1981-01-26

Family

ID=13806592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8358679A Pending JPS567467A (en) 1979-07-02 1979-07-02 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS567467A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831569A (en) * 1981-08-03 1983-02-24 テキサス・インスツルメンツ・インコ−ポレイテツド Semiconductor rom array and method of producing same
JPS58197874A (en) * 1982-05-14 1983-11-17 Nec Corp Semiconductor device and manufacture thereof
JPS59501988A (en) * 1982-11-11 1984-11-29 ハイドリル　カンパニ− Safety valve device and method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140866A (en) * 1974-10-04 1976-04-06 Nippon Electric Co HANDOTA ISOCHI
JPS5269537A (en) * 1975-12-08 1977-06-09 Fujitsu Ltd Semiconductor memory
JPS53124091A (en) * 1977-04-05 1978-10-30 Nec Corp Solid state electron device and its manufacture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140866A (en) * 1974-10-04 1976-04-06 Nippon Electric Co HANDOTA ISOCHI
JPS5269537A (en) * 1975-12-08 1977-06-09 Fujitsu Ltd Semiconductor memory
JPS53124091A (en) * 1977-04-05 1978-10-30 Nec Corp Solid state electron device and its manufacture

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831569A (en) * 1981-08-03 1983-02-24 テキサス・インスツルメンツ・インコ−ポレイテツド Semiconductor rom array and method of producing same
JPH01138747A (en) * 1981-08-03 1989-05-31 Texas Instr Inc <Ti> Polycrystalline semiconductor lateral diode
JPH0436466B2 (en) * 1981-08-03 1992-06-16 Texas Instruments Inc
JPS58197874A (en) * 1982-05-14 1983-11-17 Nec Corp Semiconductor device and manufacture thereof
JPH0332230B2 (en) * 1982-05-14 1991-05-10 Nippon Electric Co
JPS59501988A (en) * 1982-11-11 1984-11-29 ハイドリル　カンパニ− Safety valve device and method

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