JPS5754428A - Level interface circuit - Google Patents

Level interface circuit

Info

Publication number
JPS5754428A
JPS5754428A JP55129652A JP12965280A JPS5754428A JP S5754428 A JPS5754428 A JP S5754428A JP 55129652 A JP55129652 A JP 55129652A JP 12965280 A JP12965280 A JP 12965280A JP S5754428 A JPS5754428 A JP S5754428A
Authority
JP
Japan
Prior art keywords
interface circuit
level interface
drain
offset construction
drains
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55129652A
Other languages
Japanese (ja)
Inventor
Toshiyuki Misawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP55129652A priority Critical patent/JPS5754428A/en
Publication of JPS5754428A publication Critical patent/JPS5754428A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors

Landscapes

  • Logic Circuits (AREA)

Abstract

PURPOSE:To make the dielectric strength of titled circuit high, by using MOSFETs of offset construction. CONSTITUTION:A level interface circuit is constituted by using P channel MOSFETs 201, 204 forming the drains with offset construction, and N channel MOSFETs 202, 205 forming the drains with offset construction. The offsets are formed with ion implantation. The avalanche breakdown due to concentrated electric field neat the surface of the drain region in the channel and the destruction of gate oxide film due to the increase in the electric field between the gate electrode and the drain domain can be avoided. Further, the avalanche phenomenon in which the depletion layer of drain is extended to the source region can be prevented, resulting in remarkably increasing the dielectric strength of the level interface circuit.
JP55129652A 1980-09-18 1980-09-18 Level interface circuit Pending JPS5754428A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55129652A JPS5754428A (en) 1980-09-18 1980-09-18 Level interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55129652A JPS5754428A (en) 1980-09-18 1980-09-18 Level interface circuit

Publications (1)

Publication Number Publication Date
JPS5754428A true JPS5754428A (en) 1982-03-31

Family

ID=15014804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55129652A Pending JPS5754428A (en) 1980-09-18 1980-09-18 Level interface circuit

Country Status (1)

Country Link
JP (1) JPS5754428A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60237720A (en) * 1984-05-11 1985-11-26 Seiko Epson Corp Output circuit
EP0410885A2 (en) * 1989-07-25 1991-01-30 Fujitsu Limited Level-conversion semiconductor device
US7167027B2 (en) 2002-04-24 2007-01-23 Fujitsu Limited Latch-type level converter and receiver circuit accurately amplifying low-amplitude signals and receiving common-mode input signals higher than a supply voltage
JP2009147985A (en) * 2001-08-31 2009-07-02 Renesas Technology Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60237720A (en) * 1984-05-11 1985-11-26 Seiko Epson Corp Output circuit
EP0410885A2 (en) * 1989-07-25 1991-01-30 Fujitsu Limited Level-conversion semiconductor device
JP2009147985A (en) * 2001-08-31 2009-07-02 Renesas Technology Corp Semiconductor device
US7167027B2 (en) 2002-04-24 2007-01-23 Fujitsu Limited Latch-type level converter and receiver circuit accurately amplifying low-amplitude signals and receiving common-mode input signals higher than a supply voltage

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