JPS5745236A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5745236A
JPS5745236A JP55120585A JP12058580A JPS5745236A JP S5745236 A JPS5745236 A JP S5745236A JP 55120585 A JP55120585 A JP 55120585A JP 12058580 A JP12058580 A JP 12058580A JP S5745236 A JPS5745236 A JP S5745236A
Authority
JP
Japan
Prior art keywords
positioning mark
positioning
electron beam
semiconductor device
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55120585A
Other languages
Japanese (ja)
Inventor
Yoshimi Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55120585A priority Critical patent/JPS5745236A/en
Publication of JPS5745236A publication Critical patent/JPS5745236A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electron Beam Exposure (AREA)

Abstract

PURPOSE:To prevent the deterioration of positional accuracy for the subject semiconductor device by a method wherein a plurality of positioning marks, having relations with the prescribed relative positions corresponding to each chip loated on a wafer, are provided and in the case when a positioning mark is broken and deformed in each process of electron beam irradiation, other positioning mark is used. CONSTITUTION:A plurality of chips 2 are formed along a scribe line 5 on the wafer 1 and a positioning mark group, consisting of a plurality of positioning marks 4, is provided at a corner of the chip 2. In a process if electron beam irradiation, the scanning by an electron beam is performed using a positioning mark. In the case when the first positioning mark 4 is deformed by the etching and the like which was performed after the exposing process, a positioning is performed in the next exposing process using another positioning mark 4. As the interval between each positioning mark was formed at the prescribed distance in advance, the reference position for the irradiation of an electron beam can be corrected in proportion to the prescribed distance and the deterioration of the positional accuracy can be prevented.
JP55120585A 1980-09-02 1980-09-02 Manufacture of semiconductor device Pending JPS5745236A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55120585A JPS5745236A (en) 1980-09-02 1980-09-02 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55120585A JPS5745236A (en) 1980-09-02 1980-09-02 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5745236A true JPS5745236A (en) 1982-03-15

Family

ID=14789913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55120585A Pending JPS5745236A (en) 1980-09-02 1980-09-02 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5745236A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5747200A (en) * 1995-08-23 1998-05-05 Micrel, Incorporated Mask structure having offset patterns for alignment
FR2783971A1 (en) * 1998-09-30 2000-03-31 St Microelectronics Sa Semiconductor circuit with marking pattern and procedure for tool positioning with respect to its surface, comprising topographic reading and tool control by comparison to reference pattern

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5747200A (en) * 1995-08-23 1998-05-05 Micrel, Incorporated Mask structure having offset patterns for alignment
FR2783971A1 (en) * 1998-09-30 2000-03-31 St Microelectronics Sa Semiconductor circuit with marking pattern and procedure for tool positioning with respect to its surface, comprising topographic reading and tool control by comparison to reference pattern

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