JPS6450529A - Wafer alignment - Google Patents
Wafer alignmentInfo
- Publication number
- JPS6450529A JPS6450529A JP62207760A JP20776087A JPS6450529A JP S6450529 A JPS6450529 A JP S6450529A JP 62207760 A JP62207760 A JP 62207760A JP 20776087 A JP20776087 A JP 20776087A JP S6450529 A JPS6450529 A JP S6450529A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- alignment
- semiconductor wafer
- mask
- alignment mark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
PURPOSE:To make it possible to perform accurate wafer alignment with respect to both of two different layers on a semiconductor wafer, by forming first and second wafer alignment marks on the semiconductor wafer in different processes, and registering the mask with respect to the two alignment marks. CONSTITUTION:A first alignment mark 11 for positional detection in a first direction G and a second alignment mark 12 for positional detection in a second direction H are formed on a semiconductor wafer in different processes from each other, so that a mask is registered with respect to the first and second wafer alignment marks 11 and 12. According to an embodiment, the first alignment mark 11 is formed on the semiconductor wafer when a diffused layer is formed, and thereafter the second wafer alignment mark 12 is formed when a gate layer is formed. Further, before forming a contact layer on the substrate thus treated, a reticle alignment 14 is formed at a predetermined position on a mask 13 for the formation of the contact layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62207760A JPS6450529A (en) | 1987-08-21 | 1987-08-21 | Wafer alignment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62207760A JPS6450529A (en) | 1987-08-21 | 1987-08-21 | Wafer alignment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6450529A true JPS6450529A (en) | 1989-02-27 |
Family
ID=16545093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62207760A Pending JPS6450529A (en) | 1987-08-21 | 1987-08-21 | Wafer alignment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6450529A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02213117A (en) * | 1989-02-14 | 1990-08-24 | Matsushita Electron Corp | Mask aligning method for semiconductor device |
| JP2002198291A (en) * | 2000-12-26 | 2002-07-12 | Nikon Corp | Substrate, position measuring device, projection aligner, and alignment method and exposure method |
| US6448147B2 (en) * | 1998-03-27 | 2002-09-10 | Masahiro Komuro | Semiconductor device and method for manufacturing the same |
| JP2013153217A (en) * | 2005-10-31 | 2013-08-08 | Kla-Encor Corp | Method of creating scale calibration curve for overlay measurement |
-
1987
- 1987-08-21 JP JP62207760A patent/JPS6450529A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02213117A (en) * | 1989-02-14 | 1990-08-24 | Matsushita Electron Corp | Mask aligning method for semiconductor device |
| US6448147B2 (en) * | 1998-03-27 | 2002-09-10 | Masahiro Komuro | Semiconductor device and method for manufacturing the same |
| JP2002198291A (en) * | 2000-12-26 | 2002-07-12 | Nikon Corp | Substrate, position measuring device, projection aligner, and alignment method and exposure method |
| JP2013153217A (en) * | 2005-10-31 | 2013-08-08 | Kla-Encor Corp | Method of creating scale calibration curve for overlay measurement |
| JP2015039007A (en) * | 2005-10-31 | 2015-02-26 | ケーエルエー−テンカー コーポレイション | Method and device for design and use of micro target in overlay measurement |
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