JPS5743219A - Data transfer device - Google Patents

Data transfer device

Info

Publication number
JPS5743219A
JPS5743219A JP11797180A JP11797180A JPS5743219A JP S5743219 A JPS5743219 A JP S5743219A JP 11797180 A JP11797180 A JP 11797180A JP 11797180 A JP11797180 A JP 11797180A JP S5743219 A JPS5743219 A JP S5743219A
Authority
JP
Japan
Prior art keywords
register file
address
readout
data
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11797180A
Other languages
Japanese (ja)
Other versions
JPS6048783B2 (en
Inventor
Akira Jitsupou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11797180A priority Critical patent/JPS6048783B2/en
Publication of JPS5743219A publication Critical patent/JPS5743219A/en
Publication of JPS6048783B2 publication Critical patent/JPS6048783B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To increase the transfer efficiency of memory, by providing registers provided with individual address lines and data lines for readout and write-in. CONSTITUTION:At write-in, a central processor initially sets the control information to an address of a register file 203. When a request signal to a channel is taken place, a channel request reception circuit 301 makes reception at the 1st timing T0. When the control information of the register file 203 is read out at the next T0 signal, the content of the register file is renewed and data is written in a data buffer 202. At readout, the central processor initially sets the control information to the address in the register file 203. At the 2nd timing T2, the readout address of a memory request address buffer 322 is indicated and data is written in the data buffer at the next T2 signal. The T0 and T1 signals control the register file alternately to execute the readout/write-in at the same time.
JP11797180A 1980-08-27 1980-08-27 data transfer device Expired JPS6048783B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11797180A JPS6048783B2 (en) 1980-08-27 1980-08-27 data transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11797180A JPS6048783B2 (en) 1980-08-27 1980-08-27 data transfer device

Publications (2)

Publication Number Publication Date
JPS5743219A true JPS5743219A (en) 1982-03-11
JPS6048783B2 JPS6048783B2 (en) 1985-10-29

Family

ID=14724800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11797180A Expired JPS6048783B2 (en) 1980-08-27 1980-08-27 data transfer device

Country Status (1)

Country Link
JP (1) JPS6048783B2 (en)

Also Published As

Publication number Publication date
JPS6048783B2 (en) 1985-10-29

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