JPS5740930A - Formation of wiring pattern - Google Patents

Formation of wiring pattern

Info

Publication number
JPS5740930A
JPS5740930A JP11661180A JP11661180A JPS5740930A JP S5740930 A JPS5740930 A JP S5740930A JP 11661180 A JP11661180 A JP 11661180A JP 11661180 A JP11661180 A JP 11661180A JP S5740930 A JPS5740930 A JP S5740930A
Authority
JP
Japan
Prior art keywords
layer
pattern
etching
exposed
formation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11661180A
Other languages
Japanese (ja)
Inventor
Teruhiko Yamazaki
Yoshimare Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11661180A priority Critical patent/JPS5740930A/en
Publication of JPS5740930A publication Critical patent/JPS5740930A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To enable to control etching time as well as to contrive microscopic formation of a pattern by a method wherein, when an Al wiring pattern is formed on an insulating layer, the Al layer which was exposed by performing a plasma etching is removed after the oxide layer on the surface of the Al layer has been removed by performing an ion etching. CONSTITUTION:The Al layer 5 is formed on the whole surface of the insulating film layer 3, including the surface of the active region which was exposed by an aperture 4. At this time, an oxide layer 6 of aluminium oxide is formed on the surface of the Al layer by natural oxidation. On this surface, a mask pattern 7 is formed. The oxide layer 6 is removed by performing an ion etching using an Ar gas and then the exposed Al layer 5, which is not covering a mask pattern 7, is removed by performing a gas plasma ethcing using carbon tetrachloride gas. Through these procedures, the etching time can be cut down and the etching time can be controlled easily, thereby enabling to contrive microscopic formation of a pattern.
JP11661180A 1980-08-22 1980-08-22 Formation of wiring pattern Pending JPS5740930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11661180A JPS5740930A (en) 1980-08-22 1980-08-22 Formation of wiring pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11661180A JPS5740930A (en) 1980-08-22 1980-08-22 Formation of wiring pattern

Publications (1)

Publication Number Publication Date
JPS5740930A true JPS5740930A (en) 1982-03-06

Family

ID=14691452

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11661180A Pending JPS5740930A (en) 1980-08-22 1980-08-22 Formation of wiring pattern

Country Status (1)

Country Link
JP (1) JPS5740930A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03140615A (en) * 1989-10-26 1991-06-14 Timken Co:The Bearing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03140615A (en) * 1989-10-26 1991-06-14 Timken Co:The Bearing

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