JPS573161A - Memory control method - Google Patents

Memory control method

Info

Publication number
JPS573161A
JPS573161A JP7555380A JP7555380A JPS573161A JP S573161 A JPS573161 A JP S573161A JP 7555380 A JP7555380 A JP 7555380A JP 7555380 A JP7555380 A JP 7555380A JP S573161 A JPS573161 A JP S573161A
Authority
JP
Japan
Prior art keywords
data
memory
switch
busses
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7555380A
Other languages
Japanese (ja)
Inventor
Hisanori Terajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7555380A priority Critical patent/JPS573161A/en
Publication of JPS573161A publication Critical patent/JPS573161A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To achieve high-speed data transfer and processing, by making a memory dual and by providing data and address busses of two systems and a circuit which switches dual memories to busses of two systems and controls them. CONSTITUTION:Data is written from a high-speed data source 4 to a memory 2 through a switch 6, and meanwhile, a microprocessor MPU3 reads data of a memory 1 through a switch 7 and processes it. When data read and data input are completed, a switch control 8 is started by the control of the MPU3, and switches 6and 7 are switched to the contact (a) side. Then, the memory 2 is connected to an address bus 10 through the switch 7, and the memory 1 is connected to a data bus 9 through the switch 6. Consequently, data is read out from one memory while data is written to the other memory, and busses are switched when a series of this control is completed. This operation is repeated in a high speed.
JP7555380A 1980-06-06 1980-06-06 Memory control method Pending JPS573161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7555380A JPS573161A (en) 1980-06-06 1980-06-06 Memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7555380A JPS573161A (en) 1980-06-06 1980-06-06 Memory control method

Publications (1)

Publication Number Publication Date
JPS573161A true JPS573161A (en) 1982-01-08

Family

ID=13579484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7555380A Pending JPS573161A (en) 1980-06-06 1980-06-06 Memory control method

Country Status (1)

Country Link
JP (1) JPS573161A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0869431A1 (en) * 1997-04-02 1998-10-07 Oki Electric Industry Co., Ltd. Serial communication circuit
US6497897B2 (en) 1989-02-28 2002-12-24 Teijin Limited Plaster agent and method of preparing same
EP1434391A2 (en) * 2002-12-23 2004-06-30 Synad Technologies Limited Method and device for prefetching frames
GB2402513A (en) * 2003-06-05 2004-12-08 Carry Computer Eng Co Ltd Storage device with multi tiered caches for increasing transmission speeds between system and a solid state memory

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6497897B2 (en) 1989-02-28 2002-12-24 Teijin Limited Plaster agent and method of preparing same
EP0869431A1 (en) * 1997-04-02 1998-10-07 Oki Electric Industry Co., Ltd. Serial communication circuit
US6445700B1 (en) 1997-04-02 2002-09-03 Oki Electric Industry Co., Ltd. Serial communication circuit
EP1434391A2 (en) * 2002-12-23 2004-06-30 Synad Technologies Limited Method and device for prefetching frames
EP1434391A3 (en) * 2002-12-23 2008-02-20 Synad Technologies Limited Method and device for prefetching frames
GB2402513A (en) * 2003-06-05 2004-12-08 Carry Computer Eng Co Ltd Storage device with multi tiered caches for increasing transmission speeds between system and a solid state memory

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