JPS5734264A - Multiprocessor - Google Patents
MultiprocessorInfo
- Publication number
- JPS5734264A JPS5734264A JP10885480A JP10885480A JPS5734264A JP S5734264 A JPS5734264 A JP S5734264A JP 10885480 A JP10885480 A JP 10885480A JP 10885480 A JP10885480 A JP 10885480A JP S5734264 A JPS5734264 A JP S5734264A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- writing
- reading
- access
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To considerably reduce competition occurrence of an access to a common memory by reading data with a processing device with which writing and transfer of the data are performed for a memory corresponding to the common address are a of a transferred processing device. CONSTITUTION:Corresponding to a data writing operation from a processing device 1, a reading and writing selector 13 makes a writing bus 1(9) active, and accesses to a common memory 2(8). On the other hand, an access controlling circuit 16 in the memory 2(8) side makes, in a case where the device 2(2) has not accessed for reading of the memory 2(8), the writing bus 1(9) active, and accesses to the memory 2(8). Here, the circuit 16 makes, in a case where the device 2(2) has not accessed for reading of the memory 2(8), the bus 1(9) access, in addition, in a case where the device 2(2) has accessed to the memory 2(8), after completing a state of the access, the device 1(1) writes the data to the memory 2(8).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10885480A JPS5734264A (en) | 1980-08-08 | 1980-08-08 | Multiprocessor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10885480A JPS5734264A (en) | 1980-08-08 | 1980-08-08 | Multiprocessor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5734264A true JPS5734264A (en) | 1982-02-24 |
Family
ID=14495274
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10885480A Pending JPS5734264A (en) | 1980-08-08 | 1980-08-08 | Multiprocessor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5734264A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61249153A (en) * | 1985-04-26 | 1986-11-06 | Yokogawa Medical Syst Ltd | Data processor |
-
1980
- 1980-08-08 JP JP10885480A patent/JPS5734264A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61249153A (en) * | 1985-04-26 | 1986-11-06 | Yokogawa Medical Syst Ltd | Data processor |
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