JPS57203298A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS57203298A
JPS57203298A JP56088385A JP8838581A JPS57203298A JP S57203298 A JPS57203298 A JP S57203298A JP 56088385 A JP56088385 A JP 56088385A JP 8838581 A JP8838581 A JP 8838581A JP S57203298 A JPS57203298 A JP S57203298A
Authority
JP
Japan
Prior art keywords
block
time
memory array
comparator
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56088385A
Other languages
Japanese (ja)
Inventor
Tsuyoshi Shiragasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56088385A priority Critical patent/JPS57203298A/en
Priority to US06/383,838 priority patent/US4541090A/en
Publication of JPS57203298A publication Critical patent/JPS57203298A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To reduce memory capacitance at the time of tests by dividing a memory array into plural memory array blocks and providing each block with a comparator for the block test. CONSTITUTION:A memory array is divided into plural memory array blocks 3A, 3B,..., which are respectively provided wth testing comparators 9A, 9B.... If a test line 8 is turned to a high level at the time of a test, a block selecting switch 6A, 6B... and a comparator selecting switch 12A, 12B... which are corresponding to a block selected by the logical processing based upon an output of a block selecting decoder 13 are turned on. Consequently an output of a block is compared with the expected value of a data line 7 in each block and a correct or incorrect signal outputted from the corresponding comparator 9A, 9B... is fetched from an external check line 10. The processing in each array block practically reduces the memory capacitance at the time of tests, shortening the testing time.
JP56088385A 1981-06-09 1981-06-09 Semiconductor storage device Pending JPS57203298A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP56088385A JPS57203298A (en) 1981-06-09 1981-06-09 Semiconductor storage device
US06/383,838 US4541090A (en) 1981-06-09 1982-06-01 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56088385A JPS57203298A (en) 1981-06-09 1981-06-09 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS57203298A true JPS57203298A (en) 1982-12-13

Family

ID=13941321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56088385A Pending JPS57203298A (en) 1981-06-09 1981-06-09 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS57203298A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119597A (en) * 1982-12-27 1984-07-10 Fujitsu Ltd Semiconductor storage device
JPS6015899A (en) * 1983-07-08 1985-01-26 Hitachi Micro Comput Eng Ltd Storage device
JPS61158100A (en) * 1984-12-28 1986-07-17 シーメンス、アクチエンゲゼルシヤフト Integrated semiconductor memory
JPS61158099A (en) * 1984-12-28 1986-07-17 シーメンス、アクチエンゲゼルシヤフト Integrated semiconductor memory
JPS63106997A (en) * 1986-10-08 1988-05-12 シーメンス、アクチエンゲゼルシヤフト Test method and apparatus for megabit memory module
JP2015184992A (en) * 2014-03-25 2015-10-22 株式会社ジェイテクト Ram inspection method of programmable logic controller and programmable logic controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147924A (en) * 1975-06-13 1976-12-18 Fujitsu Ltd Memory unit
JPS52122446A (en) * 1976-04-07 1977-10-14 Fujitsu Ltd Circuit tester

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147924A (en) * 1975-06-13 1976-12-18 Fujitsu Ltd Memory unit
JPS52122446A (en) * 1976-04-07 1977-10-14 Fujitsu Ltd Circuit tester

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119597A (en) * 1982-12-27 1984-07-10 Fujitsu Ltd Semiconductor storage device
JPH047040B2 (en) * 1982-12-27 1992-02-07 Fujitsu Ltd
JPS6015899A (en) * 1983-07-08 1985-01-26 Hitachi Micro Comput Eng Ltd Storage device
JPS61158100A (en) * 1984-12-28 1986-07-17 シーメンス、アクチエンゲゼルシヤフト Integrated semiconductor memory
JPS61158099A (en) * 1984-12-28 1986-07-17 シーメンス、アクチエンゲゼルシヤフト Integrated semiconductor memory
JPS63106997A (en) * 1986-10-08 1988-05-12 シーメンス、アクチエンゲゼルシヤフト Test method and apparatus for megabit memory module
JP2894691B2 (en) * 1986-10-08 1999-05-24 シーメンス、アクチエンゲゼルシヤフト Method and apparatus for testing a megabit memory module
JP2015184992A (en) * 2014-03-25 2015-10-22 株式会社ジェイテクト Ram inspection method of programmable logic controller and programmable logic controller

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