JPS5563453A - Memory system - Google Patents

Memory system

Info

Publication number
JPS5563453A
JPS5563453A JP13707778A JP13707778A JPS5563453A JP S5563453 A JPS5563453 A JP S5563453A JP 13707778 A JP13707778 A JP 13707778A JP 13707778 A JP13707778 A JP 13707778A JP S5563453 A JPS5563453 A JP S5563453A
Authority
JP
Japan
Prior art keywords
address
memory unit
write
counter
auxiliary counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13707778A
Other languages
Japanese (ja)
Inventor
Hiroshi Mitsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP13707778A priority Critical patent/JPS5563453A/en
Publication of JPS5563453A publication Critical patent/JPS5563453A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To speed up the read-write cycle, by providing the auxiliary counter in the memory unit, in the memory unit in which the instruction from CPU performs readout and write-in.
CONSTITUTION: The address information obtained on the common bus 5 is written in the auxiliary counter 12 in the memory unit 2, when the address set signal obtained from CPU1 via the address set line 13 is incoming, and the counter 12 is counted up with the confirming signal on the confirmation signal line 8 from the unit 2. In reading out and write-in to continuous memory addresses, since the address designation is made at the address by the auxiliary counter 12, the access time can be reduced.
COPYRIGHT: (C)1980,JPO&Japio
JP13707778A 1978-11-04 1978-11-04 Memory system Pending JPS5563453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13707778A JPS5563453A (en) 1978-11-04 1978-11-04 Memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13707778A JPS5563453A (en) 1978-11-04 1978-11-04 Memory system

Publications (1)

Publication Number Publication Date
JPS5563453A true JPS5563453A (en) 1980-05-13

Family

ID=15190354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13707778A Pending JPS5563453A (en) 1978-11-04 1978-11-04 Memory system

Country Status (1)

Country Link
JP (1) JPS5563453A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5824954A (en) * 1981-08-06 1983-02-15 Fujitsu Ltd Address controlling system
JPS6172349A (en) * 1984-09-14 1986-04-14 Fujitsu Ltd Data transfer control system
JPS62211767A (en) * 1986-03-12 1987-09-17 Fujitsu Ltd Indirect access control system
US5459842A (en) * 1992-06-26 1995-10-17 International Business Machines Corporation System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5824954A (en) * 1981-08-06 1983-02-15 Fujitsu Ltd Address controlling system
JPH0223892B2 (en) * 1981-08-06 1990-05-25 Fujitsu Ltd
JPS6172349A (en) * 1984-09-14 1986-04-14 Fujitsu Ltd Data transfer control system
JPS62211767A (en) * 1986-03-12 1987-09-17 Fujitsu Ltd Indirect access control system
US5459842A (en) * 1992-06-26 1995-10-17 International Business Machines Corporation System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory

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