JPS57197915A - Level converting circuit - Google Patents

Level converting circuit

Info

Publication number
JPS57197915A
JPS57197915A JP8339981A JP8339981A JPS57197915A JP S57197915 A JPS57197915 A JP S57197915A JP 8339981 A JP8339981 A JP 8339981A JP 8339981 A JP8339981 A JP 8339981A JP S57197915 A JPS57197915 A JP S57197915A
Authority
JP
Japan
Prior art keywords
voltage
point
level
resistances
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8339981A
Other languages
Japanese (ja)
Other versions
JPH0311126B2 (en
Inventor
Eiji Kamihira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Ten Ltd
Original Assignee
Denso Ten Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Ten Ltd filed Critical Denso Ten Ltd
Priority to JP8339981A priority Critical patent/JPS57197915A/en
Publication of JPS57197915A publication Critical patent/JPS57197915A/en
Publication of JPH0311126B2 publication Critical patent/JPH0311126B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
    • H03K5/086—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold generated by feedback

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To evade the influence of a decrease in level in a transmission line by lowering the voltage to the input terminal of a comparing circuit, which compares the input signal with a reference voltage when the input voltage is lower than the reference voltage, and raising the input voltage when not. CONSTITUTION:When a switch 3 turns on, the voltage at a point 15 reaches 2V equal to the voltage of a voltage source 7. Since the reference voltage of a comparator 19 is 3.6V, the output of the comparator 19 drops in level and the voltage at a point 16 is 0.35V through the voltage division of resistances 12 and 13. Further, transistors 24 and 25 turn on, so the reference voltage is also divided by resistances 21, 22 and 23 to obtain 0.25V. When the switch 3 is opened, the voltage at the point 16 becomes 0.56V obtained by dividing the voltag of a power source 8 through resistances 11, 12 and 13, and the output of the comparator 19 has high impednace. Therefore, the voltage at the point 16 becomes 5V equal to the voltage of the power source 8. The voltage at the point 16 is processed by the level discrimination of a level discriminating circuit 2 to obtain a signal.
JP8339981A 1981-05-29 1981-05-29 Level converting circuit Granted JPS57197915A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8339981A JPS57197915A (en) 1981-05-29 1981-05-29 Level converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8339981A JPS57197915A (en) 1981-05-29 1981-05-29 Level converting circuit

Publications (2)

Publication Number Publication Date
JPS57197915A true JPS57197915A (en) 1982-12-04
JPH0311126B2 JPH0311126B2 (en) 1991-02-15

Family

ID=13801344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8339981A Granted JPS57197915A (en) 1981-05-29 1981-05-29 Level converting circuit

Country Status (1)

Country Link
JP (1) JPS57197915A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2411325A (en) * 2004-02-18 2005-08-24 Everspring Ind Co Ltd Rapid stabilisation of receiver slicing/thresholding at power up from battery saving sleep/power down modes

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5141949U (en) * 1974-09-21 1976-03-29
JPS5454243U (en) * 1977-09-19 1979-04-14

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5141949B2 (en) * 1971-12-28 1976-11-12

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5141949U (en) * 1974-09-21 1976-03-29
JPS5454243U (en) * 1977-09-19 1979-04-14

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2411325A (en) * 2004-02-18 2005-08-24 Everspring Ind Co Ltd Rapid stabilisation of receiver slicing/thresholding at power up from battery saving sleep/power down modes
GB2411325B (en) * 2004-02-18 2006-03-01 Everspring Ind Co Ltd Power saving circuit for transmitting signals

Also Published As

Publication number Publication date
JPH0311126B2 (en) 1991-02-15

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