JPS57188851A - Method of sealing semiconductor element - Google Patents

Method of sealing semiconductor element

Info

Publication number
JPS57188851A
JPS57188851A JP7523481A JP7523481A JPS57188851A JP S57188851 A JPS57188851 A JP S57188851A JP 7523481 A JP7523481 A JP 7523481A JP 7523481 A JP7523481 A JP 7523481A JP S57188851 A JPS57188851 A JP S57188851A
Authority
JP
Japan
Prior art keywords
hole
adhesives
cover plate
paths
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7523481A
Other languages
Japanese (ja)
Inventor
Kaoru Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7523481A priority Critical patent/JPS57188851A/en
Publication of JPS57188851A publication Critical patent/JPS57188851A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent occurrence of paths in the bonded part by a method wherein a through hole is formed in a cover plate attached on a circuit board which includes semiconductor elements mounted thereon, and after bonding the cover plate the through hole is sealed by applying adhesives. CONSTITUTION:A cover plate 6 formed with a through hole 7 is attached on a circuit board 3 which includes semiconductor elements mounted thereon, using adhesives 8. After hardening th adhesives by heating, a plate 10 is mounted on the cover plate so as to close the through hole 7. Adhesives 11 such as solder is applied to seal the through hole in a hermetic state. By so doing, it becomes possible to prevent occurrence of air holes (paths) in the adhesives 8 upon rising in temperature during the process of bonding. Thus, hermetic sealing is ensured.
JP7523481A 1981-05-18 1981-05-18 Method of sealing semiconductor element Pending JPS57188851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7523481A JPS57188851A (en) 1981-05-18 1981-05-18 Method of sealing semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7523481A JPS57188851A (en) 1981-05-18 1981-05-18 Method of sealing semiconductor element

Publications (1)

Publication Number Publication Date
JPS57188851A true JPS57188851A (en) 1982-11-19

Family

ID=13570318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7523481A Pending JPS57188851A (en) 1981-05-18 1981-05-18 Method of sealing semiconductor element

Country Status (1)

Country Link
JP (1) JPS57188851A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081327A (en) * 1990-03-28 1992-01-14 Cabot Corporation Sealing system for hermetic microchip packages
EP0921565A3 (en) * 1997-12-08 2005-07-27 Kabushiki Kaisha Toshiba Package for semiconductor power device and method for assembling the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081327A (en) * 1990-03-28 1992-01-14 Cabot Corporation Sealing system for hermetic microchip packages
EP0921565A3 (en) * 1997-12-08 2005-07-27 Kabushiki Kaisha Toshiba Package for semiconductor power device and method for assembling the same

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