JPS5718347A - Mounting structure of ic - Google Patents

Mounting structure of ic

Info

Publication number
JPS5718347A
JPS5718347A JP9285580A JP9285580A JPS5718347A JP S5718347 A JPS5718347 A JP S5718347A JP 9285580 A JP9285580 A JP 9285580A JP 9285580 A JP9285580 A JP 9285580A JP S5718347 A JPS5718347 A JP S5718347A
Authority
JP
Japan
Prior art keywords
wiring
electrode patterns
penetrating holes
electrodes
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9285580A
Other languages
Japanese (ja)
Inventor
Hayao Umemoto
Taro Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP9285580A priority Critical patent/JPS5718347A/en
Publication of JPS5718347A publication Critical patent/JPS5718347A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To perform mounting of an IC at low cost having mass productivity by a method wherein penetrating holes are provided in an insulating film formed with electrode patterns for wiring on the back face, solder balls are inserted into the holes thereof and positioning is performed, and are molten to be fixed to attain conduction between IC electrodes and the electrode patterns for wiring. CONSTITUTION:The penetrating holes 1a are formed in the insulating film 1 at the parts corresponding to the IC electrodes 3a, and the electrode patterns 2a for wiring are formed with copper foils on the back face of the film at the part corresponding to the penetrating holes. The preliminary formed solder balls 4 are inserted into the penetrating holes, and positioning is performed. The balls are molten to be fixed by gang bonding, and conductiom between the IC electrodes 3a and the electrode patterns 2a for wiring is attained. Accordingly, flowing of the solder is prevented, and equipment of the IC can be performed at low cost superior mass productivity and reliability.
JP9285580A 1980-07-08 1980-07-08 Mounting structure of ic Pending JPS5718347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9285580A JPS5718347A (en) 1980-07-08 1980-07-08 Mounting structure of ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9285580A JPS5718347A (en) 1980-07-08 1980-07-08 Mounting structure of ic

Publications (1)

Publication Number Publication Date
JPS5718347A true JPS5718347A (en) 1982-01-30

Family

ID=14066035

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9285580A Pending JPS5718347A (en) 1980-07-08 1980-07-08 Mounting structure of ic

Country Status (1)

Country Link
JP (1) JPS5718347A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0360138A (en) * 1989-07-28 1991-03-15 Nec Kansai Ltd Bonding method
JPH04299544A (en) * 1991-03-28 1992-10-22 Nec Corp Manufacture of film carrier semiconductor device
US5164336A (en) * 1989-09-11 1992-11-17 Nippon Steel Corporation Method of connecting tab tape to semiconductor chip, and bump sheet and bumped tape used in the method
JPH05251505A (en) * 1991-12-27 1993-09-28 Minnesota Mining & Mfg Co <3M> Method of connecting ic chip to area tape
JPH0722470A (en) * 1993-06-18 1995-01-24 Minnesota Mining & Mfg Co <3M> Tab tape with bump and junction using it
WO2008093373A1 (en) * 2007-02-01 2008-08-07 Cisel S.R.L. - Circuiti Stampati Per Applicazioni Elettroniche Production process of printed circuits on which electronic components without leading wire are soldered.

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0360138A (en) * 1989-07-28 1991-03-15 Nec Kansai Ltd Bonding method
US5164336A (en) * 1989-09-11 1992-11-17 Nippon Steel Corporation Method of connecting tab tape to semiconductor chip, and bump sheet and bumped tape used in the method
JPH04299544A (en) * 1991-03-28 1992-10-22 Nec Corp Manufacture of film carrier semiconductor device
JPH05251505A (en) * 1991-12-27 1993-09-28 Minnesota Mining & Mfg Co <3M> Method of connecting ic chip to area tape
JPH0722470A (en) * 1993-06-18 1995-01-24 Minnesota Mining & Mfg Co <3M> Tab tape with bump and junction using it
WO2008093373A1 (en) * 2007-02-01 2008-08-07 Cisel S.R.L. - Circuiti Stampati Per Applicazioni Elettroniche Production process of printed circuits on which electronic components without leading wire are soldered.

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