JPS57157649A - Delay shift type frame synchronizing circuit - Google Patents

Delay shift type frame synchronizing circuit

Info

Publication number
JPS57157649A
JPS57157649A JP56042300A JP4230081A JPS57157649A JP S57157649 A JPS57157649 A JP S57157649A JP 56042300 A JP56042300 A JP 56042300A JP 4230081 A JP4230081 A JP 4230081A JP S57157649 A JPS57157649 A JP S57157649A
Authority
JP
Japan
Prior art keywords
circuit
pulse
input signal
coincides
code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56042300A
Other languages
Japanese (ja)
Inventor
Hiroshi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56042300A priority Critical patent/JPS57157649A/en
Publication of JPS57157649A publication Critical patent/JPS57157649A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To shorten the time required for resetting synchronization, by separating input signals into each frame when one local frame synchronizing pulse code train continuously coincides with a synchronizing code inserted into input signals. CONSTITUTION:A frame synchronizing pulse detecting circuit 6 is constituted in such a way that, when an input signal does not coincide with any local frame synchronoizing pulse code, the detecting circuit 6 outputs a shift pulse. When one of pulse code trains outputted from a counter circuit 8 coincides with an input signal, a counter output phase selecting circuit 7 results in that the input signal may be separated by the phase of the pules code train which coincides with the input signal. The circuit 8 is controlled to send an output pulse having the phase appointed by the circuit 7 to a separating circuit.
JP56042300A 1981-03-25 1981-03-25 Delay shift type frame synchronizing circuit Pending JPS57157649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56042300A JPS57157649A (en) 1981-03-25 1981-03-25 Delay shift type frame synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56042300A JPS57157649A (en) 1981-03-25 1981-03-25 Delay shift type frame synchronizing circuit

Publications (1)

Publication Number Publication Date
JPS57157649A true JPS57157649A (en) 1982-09-29

Family

ID=12632171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56042300A Pending JPS57157649A (en) 1981-03-25 1981-03-25 Delay shift type frame synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS57157649A (en)

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