JPS57157366A - Inter-processor communication system - Google Patents
Inter-processor communication systemInfo
- Publication number
- JPS57157366A JPS57157366A JP56041706A JP4170681A JPS57157366A JP S57157366 A JPS57157366 A JP S57157366A JP 56041706 A JP56041706 A JP 56041706A JP 4170681 A JP4170681 A JP 4170681A JP S57157366 A JPS57157366 A JP S57157366A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- write
- information
- read
- prescribed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To elevate reliability of a system, by quickly communicating prescribed information to each processor by means of hardware without executing the software processing or without making it pass through an inter-processor communicating device, in a multiprocessor system. CONSTITUTION:When executing an urgent communication, for instance, a processor 10-1 sends out a write display signal to a write display line, and sets a desired urgent information to a register device 30. In this case, the write display signal of the write display line is led into a write and read-out blocking circuit so that write and read-out are not executed from other processor, and write and read-out gates corresponding to other processor are closed. The information is recorded in a prescribed bit position in the register device 30. Subsequently, each processor executes, for instance, a read-out operation of contents set in the information of the register device 30 periodically by different phase and a prescribed period. In this way, the processor 10-1 is capable of knowing whether urgent information exists or not, and also its contents, and is capable of executing its prescribed operation in accordance with the urgent information.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56041706A JPS57157366A (en) | 1981-03-24 | 1981-03-24 | Inter-processor communication system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56041706A JPS57157366A (en) | 1981-03-24 | 1981-03-24 | Inter-processor communication system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57157366A true JPS57157366A (en) | 1982-09-28 |
JPS6326422B2 JPS6326422B2 (en) | 1988-05-30 |
Family
ID=12615863
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56041706A Granted JPS57157366A (en) | 1981-03-24 | 1981-03-24 | Inter-processor communication system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57157366A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49114845A (en) * | 1973-02-28 | 1974-11-01 | ||
JPS5285443A (en) * | 1976-01-10 | 1977-07-15 | Nec Corp | Shut-off system of emergency action circuit |
-
1981
- 1981-03-24 JP JP56041706A patent/JPS57157366A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49114845A (en) * | 1973-02-28 | 1974-11-01 | ||
JPS5285443A (en) * | 1976-01-10 | 1977-07-15 | Nec Corp | Shut-off system of emergency action circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6326422B2 (en) | 1988-05-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS56140452A (en) | Memory protection system | |
FR2349886A1 (en) | DEVICE FOR PROTECTING THE CONTENT OF A MEMORY OF A DATA PROCESSING SYSTEM | |
FR2349888A1 (en) | DEVICE FOR EXTENSION OF THE MEMORY CAPACITY OF A DATA PROCESSING SYSTEM | |
FR2282676A1 (en) | SECURITY SYSTEM FOR COMPUTER MEMORY | |
BE823076A (en) | DOUBLE MEMORY REGISTRATION DEVICE FOR ELECTRONIC COMPUTER | |
JPS57157366A (en) | Inter-processor communication system | |
JPS5326632A (en) | Common memory control unit | |
JPS522330A (en) | Data processig unit | |
JPS5259537A (en) | Data processor | |
JPS5371537A (en) | Information processor | |
JPS5336A (en) | Data input unit | |
JPS5440049A (en) | Information process system | |
JPS5392638A (en) | Information processing unit | |
JPS5350628A (en) | Information processing system | |
JPS56149626A (en) | Channel device | |
JPS56129947A (en) | Microprogram controller | |
JPS5360529A (en) | Data processor | |
JPS56155453A (en) | Program execution controlling system | |
JPS5491028A (en) | Memory control system of multiprocessor system | |
JPS52104024A (en) | Information check system | |
JPS5372532A (en) | Access system for memory unit | |
JPS56157504A (en) | Control device | |
JPS52141152A (en) | Data collection system | |
JPS56121155A (en) | Address coincidence detection circuit | |
JPS52137233A (en) | Computer duplex system |