JPS56157504A - Control device - Google Patents
Control deviceInfo
- Publication number
- JPS56157504A JPS56157504A JP6187080A JP6187080A JPS56157504A JP S56157504 A JPS56157504 A JP S56157504A JP 6187080 A JP6187080 A JP 6187080A JP 6187080 A JP6187080 A JP 6187080A JP S56157504 A JPS56157504 A JP S56157504A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- control part
- detecting
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B9/00—Safety arrangements
- G05B9/02—Safety arrangements electric
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Safety Devices In Control Systems (AREA)
- Testing And Monitoring For Control Systems (AREA)
Abstract
PURPOSE:To protect a device to be controlled from errorneous control, by discriminating the malfunction of a control part to reset the control part when the phase relation between the detecting output and the synchronizing signal is shifted and disturbed. CONSTITUTION:Since a detecting signal of a specific pattern is output at a constant interval when the operation is normal, the detecting signal (a) of the specific pattern is output from a control part 1 in a position other than the normal position if the time to the next specific pattern output is shortened or extended due to program runaway, etc. This abnormality is detected by the shift of the phase between the signal (a) and the synchronizing signal (b) in a detecting circuit 4 and an NAND gate 7, and the abnormal operation is recovered. If another control signal is output from the control part 1, the control signal from an output line 3 of the control part 1 is latched in a latch 10 by the latch signal from a output line 9, and this data continues to be output to a device 2 to be controlled until the next latch signal is generated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6187080A JPS56157504A (en) | 1980-05-09 | 1980-05-09 | Control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6187080A JPS56157504A (en) | 1980-05-09 | 1980-05-09 | Control device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56157504A true JPS56157504A (en) | 1981-12-04 |
Family
ID=13183581
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6187080A Pending JPS56157504A (en) | 1980-05-09 | 1980-05-09 | Control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56157504A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6269330A (en) * | 1985-09-20 | 1987-03-30 | Matsushita Electric Ind Co Ltd | Microprocessor |
JPH0414556U (en) * | 1990-05-29 | 1992-02-05 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4861887A (en) * | 1971-12-02 | 1973-08-29 |
-
1980
- 1980-05-09 JP JP6187080A patent/JPS56157504A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4861887A (en) * | 1971-12-02 | 1973-08-29 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6269330A (en) * | 1985-09-20 | 1987-03-30 | Matsushita Electric Ind Co Ltd | Microprocessor |
JPH0414556U (en) * | 1990-05-29 | 1992-02-05 |
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