JPS57145425A - Binary data regenerating device - Google Patents

Binary data regenerating device

Info

Publication number
JPS57145425A
JPS57145425A JP3163281A JP3163281A JPS57145425A JP S57145425 A JPS57145425 A JP S57145425A JP 3163281 A JP3163281 A JP 3163281A JP 3163281 A JP3163281 A JP 3163281A JP S57145425 A JPS57145425 A JP S57145425A
Authority
JP
Japan
Prior art keywords
signal
differentiating
level
circuit
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3163281A
Other languages
Japanese (ja)
Inventor
Nobuyoshi Nakura
Taneichi Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aisin Corp
Original Assignee
Aisin Seiki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aisin Seiki Co Ltd filed Critical Aisin Seiki Co Ltd
Priority to JP3163281A priority Critical patent/JPS57145425A/en
Publication of JPS57145425A publication Critical patent/JPS57145425A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/18Error detection or correction; Testing, e.g. of drop-outs

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Digital Magnetic Recording (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To reduce the influences of a dropout and variation in tape speed by comparing a signal, obtained by differentiating an analog regenerated signal twice, with a prescribed level voltage by a voltage comparing circuit having hysteresis characteristics, and thus converting it into a binary signal. CONSTITUTION:An analog regenerated signal (a) is applied to a differentiating circuit 22, which outputs a differential signal having a peak at the inflection point of the analog regenerated signal (a). The output signal is amplified by an amplifier 23 to obtain a signal (b). This signal (b) is further applied to a differentiating circuit 24 to generate a signal (c). The signal (c) is compared with an earth level by a voltage comparing circuit 25. Consequently, even if the level of the analog regenerated signal (a) varies owing to a dropout, the inflection point is detected by differentiating it, so the variation in level causes few influences upon binary coding.
JP3163281A 1981-03-05 1981-03-05 Binary data regenerating device Pending JPS57145425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3163281A JPS57145425A (en) 1981-03-05 1981-03-05 Binary data regenerating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3163281A JPS57145425A (en) 1981-03-05 1981-03-05 Binary data regenerating device

Publications (1)

Publication Number Publication Date
JPS57145425A true JPS57145425A (en) 1982-09-08

Family

ID=12336580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3163281A Pending JPS57145425A (en) 1981-03-05 1981-03-05 Binary data regenerating device

Country Status (1)

Country Link
JP (1) JPS57145425A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489834A (en) * 1987-09-30 1989-04-05 Nec Corp Clock input circuit
GB2418484A (en) * 2004-09-24 2006-03-29 Advanced Input Devices Signal conditioning circuitry

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS495611A (en) * 1972-05-04 1974-01-18
JPS5030510A (en) * 1973-06-25 1975-03-26

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS495611A (en) * 1972-05-04 1974-01-18
JPS5030510A (en) * 1973-06-25 1975-03-26

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489834A (en) * 1987-09-30 1989-04-05 Nec Corp Clock input circuit
GB2418484A (en) * 2004-09-24 2006-03-29 Advanced Input Devices Signal conditioning circuitry
US7442915B2 (en) 2004-09-24 2008-10-28 Advanced Input Devices (Uk) Ltd Signal conditioning circuitry
GB2418484B (en) * 2004-09-24 2009-09-23 Advanced Input Devices Signal conditioning circuitry

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