JPS6489834A - Clock input circuit - Google Patents
Clock input circuitInfo
- Publication number
- JPS6489834A JPS6489834A JP62246879A JP24687987A JPS6489834A JP S6489834 A JPS6489834 A JP S6489834A JP 62246879 A JP62246879 A JP 62246879A JP 24687987 A JP24687987 A JP 24687987A JP S6489834 A JPS6489834 A JP S6489834A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- level
- signal
- comparator
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To decide the presence or absence of a clock to be inputted signal and the propriety of frequency by providing a receiver, a band pass filter, a comparator and a rectifier circuit. CONSTITUTION:A receiver 1 outputs a clock of the same frequency as the input clock frequency in receiving a clock signal 6 of a specified level or above and outputs a prescribed constant level when the level of the input signal is a specified value or below. When the clock signal 6 is within the specified frequency range, the output level of the band pass filter 3 is larger than the threshold level of the comparator 4 and a clock subjected to waveform shaping is outputted as the output of the comparator 4. The rectifier circuit 5 outputs an H level signal when the clock 14 is a prescribed level or below and has a duty ratio, and when not, the L level signal is outputted. Thus, an internal circuit 8 recognizes whether or not the normal clock is to be received.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62246879A JPH0671256B2 (en) | 1987-09-30 | 1987-09-30 | Clock input circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62246879A JPH0671256B2 (en) | 1987-09-30 | 1987-09-30 | Clock input circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6489834A true JPS6489834A (en) | 1989-04-05 |
JPH0671256B2 JPH0671256B2 (en) | 1994-09-07 |
Family
ID=17155099
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62246879A Expired - Lifetime JPH0671256B2 (en) | 1987-09-30 | 1987-09-30 | Clock input circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0671256B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06177720A (en) * | 1992-08-04 | 1994-06-24 | Samsung Semiconductor Inc | Duty-cycle control circuit of signal and supply method of clock signal provided with 50-% duty cycle |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50151034A (en) * | 1974-05-02 | 1975-12-04 | ||
JPS57145425A (en) * | 1981-03-05 | 1982-09-08 | Aisin Seiki Co Ltd | Binary data regenerating device |
JPS58144938U (en) * | 1982-03-24 | 1983-09-29 | 富士通株式会社 | Clock disconnection detection circuit |
JPS58177057A (en) * | 1982-04-09 | 1983-10-17 | Nec Corp | External clock detection and conversion circuit |
JPS59126318A (en) * | 1983-01-08 | 1984-07-20 | Fujitsu Ltd | Clock regenerating circuit |
JPS6161536A (en) * | 1984-08-31 | 1986-03-29 | Fujitsu Ltd | Timing pulse extracting circuit |
-
1987
- 1987-09-30 JP JP62246879A patent/JPH0671256B2/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50151034A (en) * | 1974-05-02 | 1975-12-04 | ||
JPS57145425A (en) * | 1981-03-05 | 1982-09-08 | Aisin Seiki Co Ltd | Binary data regenerating device |
JPS58144938U (en) * | 1982-03-24 | 1983-09-29 | 富士通株式会社 | Clock disconnection detection circuit |
JPS58177057A (en) * | 1982-04-09 | 1983-10-17 | Nec Corp | External clock detection and conversion circuit |
JPS59126318A (en) * | 1983-01-08 | 1984-07-20 | Fujitsu Ltd | Clock regenerating circuit |
JPS6161536A (en) * | 1984-08-31 | 1986-03-29 | Fujitsu Ltd | Timing pulse extracting circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06177720A (en) * | 1992-08-04 | 1994-06-24 | Samsung Semiconductor Inc | Duty-cycle control circuit of signal and supply method of clock signal provided with 50-% duty cycle |
Also Published As
Publication number | Publication date |
---|---|
JPH0671256B2 (en) | 1994-09-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ATE21216T1 (en) | TRANSCUTANEOUS SIGNAL TRANSMISSION SYSTEM. | |
GB2229609B (en) | Radio communication system | |
JPS6449303A (en) | Wide band mixer | |
TW265488B (en) | Decimation filter having a selectable decimation ratio | |
ES8704686A1 (en) | Circuit for producing a criterion for reception. | |
JPS6489834A (en) | Clock input circuit | |
EP0090314A3 (en) | Pcm encoder conformable to the a-law | |
ATE195832T1 (en) | CIRCUIT ARRANGEMENT FOR ATTENUATION OF A DIGITAL AUDIO SIGNAL DURING THE OCCURANCE OF SHORT-TERM DISTURBANCES | |
JPS5799062A (en) | Reception circuit for data transmission | |
JPS647813A (en) | Automatic threshold level setting circuit | |
JPS5731256A (en) | Ncu circuit | |
JPS56115024A (en) | Automatic threshold level setting circuit | |
JPS53116017A (en) | Automatic frequency control system for ssb receivers | |
JPS5468103A (en) | Receiver for multi-frequency signal | |
JPS56108968A (en) | Measuring method for center frequency of narrow band irregular signal | |
EP0262659A3 (en) | Receiver | |
JPS56156091A (en) | Remote control method | |
JPS5720832A (en) | Interruption input circuit | |
JPS5630327A (en) | Antenna circuit | |
JPS6410742A (en) | Digital signal transmission system | |
JPS6416078A (en) | Noise reduction circuit | |
JPS55104188A (en) | Pb signal reception system | |
JPS5590154A (en) | Timing regenerating circuit | |
JPS57133756A (en) | Audio switch circuit | |
JPS6460025A (en) | Transmitting/receiving device for communication |