JPS57141936A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57141936A
JPS57141936A JP2651381A JP2651381A JPS57141936A JP S57141936 A JPS57141936 A JP S57141936A JP 2651381 A JP2651381 A JP 2651381A JP 2651381 A JP2651381 A JP 2651381A JP S57141936 A JPS57141936 A JP S57141936A
Authority
JP
Japan
Prior art keywords
wiring
contact hole
sih4
wirings
breaking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2651381A
Other languages
Japanese (ja)
Inventor
Tsutomu Tsuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2651381A priority Critical patent/JPS57141936A/en
Publication of JPS57141936A publication Critical patent/JPS57141936A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To prevent the breaking of wire of the underlayer wiring to be connected and to obtain high reliability for the subject semiconductor device by a method wherein an insulating film, consisting of a metal compound to be provided on an underlying wiring, is formed in such a manner that a metal ingredient will gradually become low-densed as it approached the upper part of the wiring, and the section of a contact hole is formed in a cone shape. CONSTITUTION:For example, an underlying wiring layer 22 is formed on a GaAs substrate 21, and a nitride film 23 is formed on the wiring layer 22 by decompression CVD method using SiH4/NH3 reaction gas, for example. The nitride film 23 is deposited in such a manner that the density of an Si ingredient will be gradually reduced as it approaches the upper part by slowly reducing the quantity of flow of SiH4, for example. Then, a photoetching is performed on a contact hole 24 using a resist film 27, for example, as a mask, subsequently resist film 27 is removed, and the wirings are connected by providing an upperlayer wiring. Accordingly, the shape of the section of the contact hole 24 can be formed into a gently-sloped cone shape, and the trouble casued by the breaking of wire and the like of the wirings on the upper layer can be prevented.
JP2651381A 1981-02-25 1981-02-25 Semiconductor device Pending JPS57141936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2651381A JPS57141936A (en) 1981-02-25 1981-02-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2651381A JPS57141936A (en) 1981-02-25 1981-02-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57141936A true JPS57141936A (en) 1982-09-02

Family

ID=12195551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2651381A Pending JPS57141936A (en) 1981-02-25 1981-02-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57141936A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100388575C (en) * 2003-03-17 2008-05-14 北京邮电大学 Method for making structure of wedge chamber and parallel chamber in indium phosphide based photoelectronic device
US20170170357A1 (en) * 2011-11-25 2017-06-15 Saint-Augustin Canada Electric Inc. Method for preventing an electrical shortage in a semiconductor layer stack, thin substrate cpv cell, and solar cell assembly

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100388575C (en) * 2003-03-17 2008-05-14 北京邮电大学 Method for making structure of wedge chamber and parallel chamber in indium phosphide based photoelectronic device
US20170170357A1 (en) * 2011-11-25 2017-06-15 Saint-Augustin Canada Electric Inc. Method for preventing an electrical shortage in a semiconductor layer stack, thin substrate cpv cell, and solar cell assembly

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