JPS5485671A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5485671A
JPS5485671A JP15402977A JP15402977A JPS5485671A JP S5485671 A JPS5485671 A JP S5485671A JP 15402977 A JP15402977 A JP 15402977A JP 15402977 A JP15402977 A JP 15402977A JP S5485671 A JPS5485671 A JP S5485671A
Authority
JP
Japan
Prior art keywords
layer
film
electrode
sio
bump electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15402977A
Other languages
Japanese (ja)
Inventor
Hiroyasu Karimoto
Masaru Yamamoto
Kosei Kajiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15402977A priority Critical patent/JPS5485671A/en
Publication of JPS5485671A publication Critical patent/JPS5485671A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To reduce the probability of open wire due to Al corrosion, even with the surface insulation damaged, by providing the bump electrode in common use through a plurality of Al wires lead out which are separated from the diffusion layer of the substrate.
CONSTITUTION: The SiO2 film 51 is opened 53, 53' on the diffusion layer 52 of the n or p type substrate 50. Two wiring patterns 54, 54' are formed by separation by evaporating Al on the entire surface. The ohmic connection of Al and Si is formed with sintering for 30 minutes at 500°C under N2, covering the CVD SiO2 55. Next, the Cr-Cu layer 57 is formed by opening 56, 56' on the A° wires 54, 54' and the film 55. The bump electrode 58 is formed with gold plating by taking the layer 57 as electrode through the use of resist mask. When the layer 57 is etched by selectively forming another resist mask through removing the mask, the electrode 58 is finished. With this constitution, even if the Al wiring is collided with the etching solution of the barrier metal 27 with the crack of SiO2 film, the probability interrupting the bump electrode and element connection can remarkably be less and the yield rate is increased.
COPYRIGHT: (C)1979,JPO&Japio
JP15402977A 1977-12-20 1977-12-20 Semiconductor device Pending JPS5485671A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15402977A JPS5485671A (en) 1977-12-20 1977-12-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15402977A JPS5485671A (en) 1977-12-20 1977-12-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5485671A true JPS5485671A (en) 1979-07-07

Family

ID=15575342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15402977A Pending JPS5485671A (en) 1977-12-20 1977-12-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5485671A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607758A (en) * 1983-06-27 1985-01-16 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607758A (en) * 1983-06-27 1985-01-16 Nec Corp Semiconductor device

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