JPS5712536A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5712536A
JPS5712536A JP8703180A JP8703180A JPS5712536A JP S5712536 A JPS5712536 A JP S5712536A JP 8703180 A JP8703180 A JP 8703180A JP 8703180 A JP8703180 A JP 8703180A JP S5712536 A JPS5712536 A JP S5712536A
Authority
JP
Japan
Prior art keywords
layer
eliminating
alloyed
joint
approximately
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8703180A
Other languages
Japanese (ja)
Inventor
Hiroaki Okizaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8703180A priority Critical patent/JPS5712536A/en
Publication of JPS5712536A publication Critical patent/JPS5712536A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve reliability of a device, by eliminating a semiconductor layer and a metallic layer on an element-formed substrate and heat-treating thus laminated product to turn it into an alloy, and then, by eliminating the alloyed layer and the metallic layer selectively. CONSTITUTION:A window is selectively provided on an SiO25 for protection of a P-N joint and surface, and an Si layer 6 with a thickness of approximately 300- 500Angstrom and Al7 of approximately 2mu are laminated. Impurity-containing Si, poly Si or any other semiconductor may well be used for the layer 6. Further, Mo, Ti and W, etc. may be used instead of Al. And then, thus prepared product is heat-treated at a temperature ranging from 350-500 deg.C to be alloyed, and the layers 7 and 9 are etched out with a resist mask 8 to complete wiring layers 9-11. It is possible, by using this mechanism, to prevent occurrence of P-N joint shortcircuit as Al does not contact an element section directily and improve reliability of the device, and besides, it also possible to shorten manufacturing process.
JP8703180A 1980-06-26 1980-06-26 Manufacture of semiconductor device Pending JPS5712536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8703180A JPS5712536A (en) 1980-06-26 1980-06-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8703180A JPS5712536A (en) 1980-06-26 1980-06-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5712536A true JPS5712536A (en) 1982-01-22

Family

ID=13903578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8703180A Pending JPS5712536A (en) 1980-06-26 1980-06-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5712536A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system

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