JPS57120399A - Multilayer printed circuit board and method of detecting actual position of connecting surface - Google Patents
Multilayer printed circuit board and method of detecting actual position of connecting surfaceInfo
- Publication number
- JPS57120399A JPS57120399A JP56192700A JP19270081A JPS57120399A JP S57120399 A JPS57120399 A JP S57120399A JP 56192700 A JP56192700 A JP 56192700A JP 19270081 A JP19270081 A JP 19270081A JP S57120399 A JPS57120399 A JP S57120399A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- actual position
- multilayer printed
- connecting surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2805—Bare printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0008—Apparatus or processes for manufacturing printed circuits for aligning or positioning of tools relative to the circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49004—Electrical device making including measuring or testing of device or component part
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Laminated Bodies (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19803045433 DE3045433A1 (de) | 1980-12-02 | 1980-12-02 | Mehrlagen-leiterplatte und verfahren zur ermittlung der ist-position innenliegender anschlussflaechen |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57120399A true JPS57120399A (en) | 1982-07-27 |
JPH0413880B2 JPH0413880B2 (ja) | 1992-03-11 |
Family
ID=6118134
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56192700A Granted JPS57120399A (en) | 1980-12-02 | 1981-11-30 | Multilayer printed circuit board and method of detecting actual position of connecting surface |
Country Status (4)
Country | Link |
---|---|
US (1) | US4432037A (ja) |
EP (1) | EP0053272B2 (ja) |
JP (1) | JPS57120399A (ja) |
DE (1) | DE3045433A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015166587A1 (ja) * | 2014-05-02 | 2015-11-05 | 株式会社メイコー | 回路基板の製造方法 |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3206354A1 (de) * | 1982-02-22 | 1983-09-01 | Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt | Vorrichtung zum aendern oder reparieren von nicht sichtbaren leiterbahnmustern von mehrlagigen leiterplatten |
US4510446A (en) * | 1982-11-03 | 1985-04-09 | Burroughs Corporation | Test coupons for determining the registration of subsurface layers in a multilayer printed circuit board |
DE3347991C2 (en) * | 1983-03-01 | 1988-01-07 | Held, Kurt, 7218 Trossingen, De | Method and device for the continuous production of multilayer circuits |
DE3307057C2 (de) | 1983-03-01 | 1991-02-14 | Held, Kurt, 7218 Trossingen | Vorrichtung zur kontinuierlichen Herstellung kupferkaschierter Elektrolaminate |
US4536239A (en) * | 1983-07-18 | 1985-08-20 | Nicolet Instrument Corporation | Multi-layer circuit board inspection system |
US4700214A (en) * | 1983-12-15 | 1987-10-13 | Laserpath Corporation | Electrical circuitry |
WO1985002751A1 (en) * | 1983-12-15 | 1985-06-20 | Laserpath Corporation | Partially aligned multi-layered circuitry |
US4720470A (en) * | 1983-12-15 | 1988-01-19 | Laserpath Corporation | Method of making electrical circuitry |
JPS61125712A (ja) * | 1984-11-26 | 1986-06-13 | Matsushita Electric Works Ltd | 多層印刷配線板の孔穿設法 |
IT1201315B (it) * | 1985-06-17 | 1989-01-27 | M A S Ind Spa | Metodo per assicurare il raffreddamento di componenti elettronici fissati su di un multistrato per circuiti stampati e multistrato realizzato secondo detto metodo |
US4769309A (en) * | 1986-10-21 | 1988-09-06 | Westinghouse Electric Corp. | Printed circuit boards and method for manufacturing printed circuit boards |
DE3642926A1 (de) * | 1986-12-16 | 1988-06-30 | Siemens Ag | Anordnung und verfahren zum erkennen des innenlagenversatzes von mehrlagenleiterplatten |
US4894606A (en) * | 1988-07-07 | 1990-01-16 | Paur Tom R | System for measuring misregistration of printed circuit board layers |
US4918380A (en) * | 1988-07-07 | 1990-04-17 | Paur Tom R | System for measuring misregistration |
US4939469A (en) * | 1988-08-01 | 1990-07-03 | Hughes Aircraft Company | Non-destructive method for evaluation of printed wiring boards |
US5028867A (en) * | 1989-08-31 | 1991-07-02 | Nippon Seiki Co., Ltd. | Printed-wiring board |
DE3936723A1 (de) * | 1989-11-04 | 1991-05-08 | Loehr & Herrmann Gmbh | Vorrichtung zum selbsttaetigen positionieren von leiterplatten |
US4973948A (en) * | 1990-01-26 | 1990-11-27 | Micron Technology, Inc. | Reversed or missing lead frame detector |
US4985675A (en) * | 1990-02-13 | 1991-01-15 | Northern Telecom Limited | Multi-layer tolerance checker |
DE4016088C2 (de) * | 1990-05-18 | 1996-04-18 | Siemens Nixdorf Inf Syst | Verfahren zum Bohren von Mehrlagenleiterplatten |
ATE114262T1 (de) * | 1991-09-17 | 1994-12-15 | Siemens Nixdorf Inf Syst | Verfahren zum bohren von mehrlagenleiterplatten. |
JPH05235557A (ja) * | 1992-02-21 | 1993-09-10 | N P S Kk | 位置ずれ量測定システム |
DE4335879B4 (de) * | 1993-10-18 | 2005-05-12 | Shf Communication Technologies Ag | Anordnung zur Qualitätskontrolle und -überwachung von durchkontaktierten Mehrlagen-Leiterplatten |
EP0669792B1 (en) * | 1994-02-28 | 1999-12-22 | Cybernetics Products, Inc. | Drill coordinate optimization for multi-layer printed circuit board |
NL1001113C2 (nl) * | 1995-09-01 | 1997-03-04 | Henricus Dethmer Ubbo Ubbens | Werkwijze voor het bepalen van onderlinge posities van een aantal lagen van een meerlaags printpaneel, inrichting geschikt voor het uitvoeren van een dergelijke wijze alsmede meetstift en printpaneel geschikt voor toepassing bij een dergelijke werkwijze. |
DE19534313C2 (de) * | 1995-09-15 | 2000-02-03 | Imr Electronic Gmbh & Co Kg | Verfahren zur Erfassung von Position und Versatz von Lagen an Mehrlagenleiterplatten |
US6297458B1 (en) | 1999-04-14 | 2001-10-02 | Dell Usa, L.P. | Printed circuit board and method for evaluating the inner layer hole registration process capability of the printed circuit board manufacturing process |
US6502302B2 (en) * | 2000-07-19 | 2003-01-07 | Ngk Insulators, Ltd. | Process for producing an industrial member having throughholes of high aspect ratio |
US6637102B2 (en) | 2000-07-19 | 2003-10-28 | Ngk Insulators, Ltd. | Process for producing an industrial member having throughholes of high aspect ratio |
DE10040303C2 (de) * | 2000-08-17 | 2002-07-11 | Volker Nissen | Verfahren zum definierten Tiefenbohren von Sacklöchern (blind vias) in mehrlagigen Leiterplatten (Multilayer) |
JP4172920B2 (ja) * | 2001-04-27 | 2008-10-29 | 日本碍子株式会社 | 打抜加工のカス取り方法及び打抜加工品の製造方法 |
JP2007522662A (ja) * | 2004-02-17 | 2007-08-09 | 日立ビアメカニクス株式会社 | 基板の製造方法 |
AT501513B1 (de) * | 2005-03-01 | 2007-06-15 | Austria Tech & System Tech | Mehrlagige leiterplatte mit leitenden testflächen sowie verfahren zum bestimmen eines versatzes einer innenlage |
JP5018840B2 (ja) * | 2009-07-27 | 2012-09-05 | 富士通株式会社 | クーポン基板 |
US9297795B2 (en) | 2010-12-03 | 2016-03-29 | Todd Nicholas Bishop | Monitored filament insertion for resitivity testing |
CN102413633B (zh) * | 2011-11-03 | 2014-04-30 | 华为技术有限公司 | 一种检测多层电路板偏位的装置及方法 |
DE102013004679B4 (de) * | 2013-03-19 | 2017-11-23 | Skybrain Vermögensverwaltung GmbH | Vorrichtung und Verfahren zum Bearbeiten von Leiterplatten |
US9368936B1 (en) | 2013-09-30 | 2016-06-14 | Google Inc. | Laser diode firing system |
CN105848427B (zh) * | 2015-01-14 | 2019-01-18 | 深南电路股份有限公司 | Pcb板的钻孔方法、检验pcb板钻孔偏位的方法、pcb板及设备 |
CN105764241A (zh) * | 2016-03-23 | 2016-07-13 | 中国航天科技集团公司第九研究院第七七研究所 | 一种印制板产品对准度测试方法 |
TWI826105B (zh) * | 2022-11-07 | 2023-12-11 | 八目科技有限公司 | 量測電路板之對位方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5445363U (ja) * | 1977-09-06 | 1979-03-29 | ||
JPS55102300A (en) * | 1980-01-21 | 1980-08-05 | Hitachi Ltd | Method of detecting inner layer pattern position for multilayer printed board |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3428872A (en) * | 1965-07-31 | 1969-02-18 | Hitachi Ltd | Body comprising a mark for indirect detection of an objective part and method of detecting the position of said objective part |
US3859711A (en) * | 1973-03-20 | 1975-01-14 | Ibm | Method of detecting misregistration of internal layers of a multilayer printed circuit panel |
US3917983A (en) * | 1973-11-12 | 1975-11-04 | Bunker Ramo | Multiwafer electrical circuit construction and method of making |
US4048438A (en) * | 1974-10-23 | 1977-09-13 | Amp Incorporated | Conductor patterned substrate providing stress release during direct attachment of integrated circuit chips |
US4049903A (en) * | 1974-10-23 | 1977-09-20 | Amp Incorporated | Circuit film strip and manufacturing method |
DE2553734A1 (de) * | 1975-11-29 | 1977-06-02 | Gerhard Dipl Phys Kessling | Vorrichtung zum herstellen von lochungen in gedruckten schaltungen |
US4063791A (en) * | 1976-12-27 | 1977-12-20 | Cutchaw John M | Connector for leadless integrated circuit packages |
DE2812976C2 (de) * | 1978-03-23 | 1980-03-06 | Erich Ing.(Grad.) 3003 Ronnenberg Luther | Verfahren zur Feststellung des Versatzes zwischen Leiterbahnen und Kontaktlöchern bei einer Leiterplatte sowie eine Leiterplatte zur Verwendung in diesem Verfahren |
DE3031103C2 (de) * | 1980-08-16 | 1982-08-19 | Bodenseewerk Gerätetechnik GmbH, 7770 Überlingen | Verfahren zur Prüfung des Lageversatzes bei Mehrlagenleiterplatten |
-
1980
- 1980-12-02 DE DE19803045433 patent/DE3045433A1/de active Granted
-
1981
- 1981-10-23 EP EP81108820A patent/EP0053272B2/de not_active Expired
- 1981-10-26 US US06/315,038 patent/US4432037A/en not_active Expired - Lifetime
- 1981-11-30 JP JP56192700A patent/JPS57120399A/ja active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5445363U (ja) * | 1977-09-06 | 1979-03-29 | ||
JPS55102300A (en) * | 1980-01-21 | 1980-08-05 | Hitachi Ltd | Method of detecting inner layer pattern position for multilayer printed board |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015166587A1 (ja) * | 2014-05-02 | 2015-11-05 | 株式会社メイコー | 回路基板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP0053272B1 (de) | 1986-04-16 |
EP0053272B2 (de) | 1989-11-08 |
DE3045433A1 (de) | 1982-07-01 |
EP0053272A2 (de) | 1982-06-09 |
US4432037A (en) | 1984-02-14 |
JPH0413880B2 (ja) | 1992-03-11 |
EP0053272A3 (en) | 1983-04-27 |
DE3045433C2 (ja) | 1989-07-20 |
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