JPH025050B2 - - Google Patents
Info
- Publication number
- JPH025050B2 JPH025050B2 JP55185806A JP18580680A JPH025050B2 JP H025050 B2 JPH025050 B2 JP H025050B2 JP 55185806 A JP55185806 A JP 55185806A JP 18580680 A JP18580680 A JP 18580680A JP H025050 B2 JPH025050 B2 JP H025050B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- signal
- pulse
- input signal
- pulse modulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000000087 stabilizing effect Effects 0.000 claims description 5
- 230000006641 stabilisation Effects 0.000 claims description 4
- 238000011105 stabilization Methods 0.000 claims description 4
- 239000000284 extract Substances 0.000 claims 1
- 230000010354 integration Effects 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 10
- 238000001514 detection method Methods 0.000 description 5
- 238000000605 extraction Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
Landscapes
- Facsimile Image Signal Circuits (AREA)
- Manipulation Of Pulses (AREA)
Description
【発明の詳細な説明】
本発明はパルス変調してアナログ信号を伝送す
るパルス変調器の周波数安定化装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency stabilizing device for a pulse modulator that transmits analog signals by pulse modulation.
デイジタル伝送技術の発達に伴い、画像信号等
のアナログ信号をパルス変調器を用いてパルス変
調して伝送することが行われている。この種のパ
ルス変調器には、パルス周波数変調（PFM），パ
ルス位置変調（PPM），パルス間隔変調（PIM）
等の各種方式のものがあるが、これらの変調器に
てアナログ信号をパルス変調する場合、パルス変
調出力の周波数安定性が問題となる。パルス変調
出力の周波数変動は、例えば変調器の動作電圧の
変動や、動作環境の温度変動等によつて生じるも
ので、従来よりこれを補償する為に各種の対策が
講じられている。一般的には変調器本体に組込ま
れる各種定電圧源や定電流源の温度や電圧変動に
対する補償を行つたり、信号変調に用いられる積
分用コンデンサの温度補償を行う等の対策が講じ
られる。然乍ら、このような従来方式による対策
では、広い範囲に亘る温度変動や電圧変動に対し
て十分に機能させることが困難であり、高精度な
周波数安定化が望めなかつた。しかも長期間に亘
る安定化を図ることも極めて困難であつた。 With the development of digital transmission technology, analog signals such as image signals are pulse-modulated using a pulse modulator and then transmitted. This type of pulse modulator includes pulse frequency modulation (PFM), pulse position modulation (PPM), and pulse interval modulation (PIM).
There are various types of modulators, but when pulse modulating an analog signal using these modulators, the frequency stability of the pulse modulation output becomes a problem. Frequency fluctuations in the pulse modulation output are caused by, for example, fluctuations in the operating voltage of the modulator, fluctuations in the temperature of the operating environment, etc., and various measures have been taken to compensate for this. Generally, measures are taken to compensate for temperature and voltage fluctuations in various constant voltage sources and constant current sources built into the modulator body, and to compensate for the temperature of an integrating capacitor used for signal modulation. Naturally, with such conventional countermeasures, it is difficult to function sufficiently against temperature fluctuations and voltage fluctuations over a wide range, and highly accurate frequency stabilization cannot be expected. Furthermore, it was extremely difficult to achieve long-term stability.
本発明はこのような事情を考慮してなされたも
ので、その目的とするところは、簡易な制御によ
つて長期に亘る高精度な周波数の安定化を図るこ
とのできるパルス変調器の周波数安定化装置を提
供することにある。 The present invention has been made in consideration of these circumstances, and its purpose is to provide frequency stabilization of a pulse modulator that can stabilize the frequency with high precision over a long period of time through simple control. The objective is to provide a device for converting
以下、図面を参照して本発明の一実施例につき
説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図はパルス変調器と、その周波数安定化装
置を示す概略構成図である。 FIG. 1 is a schematic configuration diagram showing a pulse modulator and its frequency stabilizing device.
パルス変調器１は、パルス周波数変調器やパル
ス位置変調器やパルス間隔変調器等により、信号
の伝送仕様に応じて実現されるものであるが、こ
こではパルス周波数変調器を用い、アナログ信号
である画像信号をパルス周波数変調するものとし
て説明する。 The pulse modulator 1 is implemented using a pulse frequency modulator, pulse position modulator, pulse interval modulator, etc. according to the signal transmission specifications. An explanation will be given assuming that a certain image signal is subjected to pulse frequency modulation.
画像信号はクランプ回路２を介し、所定レベル
でクランプして入力される。クランプ回路２は、
上記入力画像信号の平均画像レベル（APL）が
変化した場合であつても、その同期信号レベルを
一定に規定するものである。しかして、このクラ
ンプ回路２を介して入力された画像信号は、加算
器３を介し、後述する誤差信号が加えられたのち
パルス変調器（PFM）１に入力されてパルス周
波数変調されて出力される。また上記画像信号は
同期信号抽出回路４に導かれ、同画像信号中に含
まれる同期信号の抽出が行われている。この同期
信号抽出回路４にて、同期信号、つまり基準レベ
ル信号期間の検出が行われることになる。 The image signal is input via the clamp circuit 2 after being clamped at a predetermined level. The clamp circuit 2 is
Even if the average image level (APL) of the input image signal changes, the synchronization signal level is defined to be constant. The image signal inputted through this clamp circuit 2 is then inputted to a pulse modulator (PFM) 1 after being added with an error signal (to be described later) via an adder 3, where it is pulse frequency modulated and output. Ru. The image signal is also led to a synchronization signal extraction circuit 4, where the synchronization signal contained in the image signal is extracted. The synchronization signal extraction circuit 4 detects the synchronization signal, that is, the reference level signal period.
ところで、前記パルス変調器１のパルス変調出
力信号はデユーテイ補正回路５に導かれ、デユー
テイ比１：１のパルス信号に変換されて、上記変
調信号の周波数成分を示すパルス信号に正規化さ
れている。また基準周波数発生器６は、比較基準
となる周波数のパルス信号を発生しており、この
信号はデユーテイ補正回路７に導びかれて、先の
変調信号と同様にデユーテイ比１：１のパルス信
号に変換されている。この比較基準周波数のパル
ス信号と前記変調出力の正規化されたパルス信号
とがデイジタル位相比較器８にてその周波数比較
がなされている。位相比較器８は、変調出力の周
波数a、基準信号の周波数をbとしたとき、そ
の大小関係、つまりa＞bを判定検出している。
そして、上記周波数判定結果に従つてその周波数
誤差に相当した判定出力信号ａまたはｂを発生し
ている。 By the way, the pulse modulation output signal of the pulse modulator 1 is led to the duty correction circuit 5, where it is converted into a pulse signal with a duty ratio of 1:1 and normalized into a pulse signal representing the frequency component of the modulation signal. . Further, the reference frequency generator 6 generates a pulse signal with a frequency that serves as a comparison standard, and this signal is led to the duty correction circuit 7, and is then converted into a pulse signal with a duty ratio of 1:1, similar to the previous modulation signal. has been converted to A digital phase comparator 8 compares the frequencies of the pulse signal of this comparison reference frequency and the normalized pulse signal of the modulated output. The phase comparator 8 determines and detects the magnitude relationship, that is, a>b, where the frequency of the modulated output is a and the frequency of the reference signal is b.
Then, according to the frequency determination result, a determination output signal a or b corresponding to the frequency error is generated.
しかして上記判定出力信号ａ，ｂは前記同期信
号抽出回路４の出力によりスイツチング制御され
るスイツチ回路９を介してチヤージポンプ回路１
０に供給される。スイツチ回路９は、アナログス
イツチ９ａ，９ｂにて上記判定出力信号をゲーテ
イングし、ゲート期間のみこれをチヤージポンプ
回路１０に与えるものである。即ち、同期信号抽
出回路４は前述したように基準レベル信号期間を
検出しており、この期間において上記スイツチ回
路９による判定出力信号のゲート入力が行われる
ようになつている。 The judgment output signals a and b are then sent to the charge pump circuit 1 via a switch circuit 9 which is controlled by the output of the synchronization signal extraction circuit 4.
0. The switch circuit 9 gates the judgment output signal using analog switches 9a and 9b, and supplies it to the charge pump circuit 10 only during the gate period. That is, the synchronizing signal extraction circuit 4 detects the reference level signal period as described above, and the gate input of the judgment output signal by the switch circuit 9 is performed during this period.
チヤージポンプ回路１０は、例えば上記判定出
力信号ａ，ｂによりON動作するアナログスイツ
チ１０ａ，１０ｂを縦続に接続し、その両端に電
源を接続して上記アナログスイツチ１０ａ，１０
ｂの接続点に接続された充放電用のコンデンサ１
１を充放電するべく構成されている。これによつ
てコンデンサ１１にはa＜bなる条件のときプ
ラスの電荷が充電され、逆にa＞bなる条件の
ときにはマイナスの電荷が充電される。このよう
なコンデンサ１１への電荷の充放電は前記基準レ
ベル期間、つまり一定期間のみ行われ、従つてコ
ンデンサ１１により上記周波数誤差に応じた電荷
が上記基準レベル期間に瓦つて積分され、その積
分値が充電電荷として蓄えられることになる。そ
してこのようにしてコンデンサ１１に蓄えられた
電荷により示される充電電圧がチヤーポンプ回路
１０の出力として低域波器１２を介して前記加
算器３に帰還入力されて、入力画像信号に加えら
れる。 The charge pump circuit 10 includes, for example, analog switches 10a and 10b connected in cascade that are turned ON by the above-mentioned judgment output signals a and b, and a power supply connected to both ends of the analog switches 10a and 10b.
Capacitor 1 for charging and discharging connected to the connection point b
1 is configured to charge and discharge. As a result, the capacitor 11 is charged with a positive charge when the condition a<b, and conversely with a negative charge when the condition a>b. Such charging and discharging of electric charge to the capacitor 11 is performed only during the reference level period, that is, for a certain period of time. Therefore, the electric charge corresponding to the frequency error is integrated by the capacitor 11 during the reference level period, and the integrated value is obtained. will be stored as charge. The charging voltage represented by the charge stored in the capacitor 11 in this manner is fed back to the adder 3 as an output of the charge pump circuit 10 via the low frequency amplifier 12, and is added to the input image signal.
このような周波数誤差検出が、基準レベル信号
期間が検出される都度行われる。そして、チヤー
ジポンプ回路１０に充電された誤差信号が入力画
像信号に加えられ、次の検出タイミングでは、上
記誤差信号が加えられた信号に対して周波数誤差
検出が行われる。従つて、上記周波数誤差検出が
基準レベル信号期間の検出の都度繰返えされるこ
とによつて、チヤージポンプ回路１０のコンデン
サ１１の充電電圧は、周波数誤差に相当した値に
収束する。しかるのちには、チヤージポンプ回路
１０の出力が加えられ、そのパルス変調出力の周
波数が基準周波数と等しくなるので、チヤージポ
ンプ回路１０におけるコンデンサ１１の充電電圧
は一定に保持される。これによつて基準レベル入
力に対するパルス変調出力の周波数が基準周波数
に等しく一定化され、ここにパルス変調器１の周
波数安定化が行われることになる。 Such frequency error detection is performed each time a reference level signal period is detected. Then, the error signal charged in the charge pump circuit 10 is added to the input image signal, and at the next detection timing, frequency error detection is performed on the signal to which the error signal is added. Therefore, by repeating the frequency error detection each time the reference level signal period is detected, the charging voltage of the capacitor 11 of the charge pump circuit 10 converges to a value corresponding to the frequency error. Thereafter, the output of the charge pump circuit 10 is added, and the frequency of the pulse modulated output becomes equal to the reference frequency, so that the charging voltage of the capacitor 11 in the charge pump circuit 10 is held constant. As a result, the frequency of the pulse modulation output with respect to the reference level input is made constant to be equal to the reference frequency, and the frequency of the pulse modulator 1 is thereby stabilized.
また何らかの原因によつてパルス変調器１の動
作状態が変動し、これによつて変調出力の周波数
が変動した場合には、この周波数変動に応じて位
相比較器８が判定信号ａまたはｂを出力してチヤ
ージポンプ回路１０におけるコンデンサ１１の充
電電圧が可変されるので、周波数変動に追従して
その補正が行われることになる。故に、長期に亘
つてパルス変調周波数の高精度な安定化が図られ
ることになる。 Furthermore, if the operating state of the pulse modulator 1 fluctuates for some reason and the frequency of the modulated output fluctuates as a result, the phase comparator 8 outputs the determination signal a or b in accordance with this frequency fluctuation. As a result, the charging voltage of the capacitor 11 in the charge pump circuit 10 is varied, so that correction is performed to follow frequency fluctuations. Therefore, the pulse modulation frequency can be stabilized with high accuracy over a long period of time.
以上、説明したように本装置によれば、比較的
簡単な制御により、高精度に変調周波数の安定化
を図ることができる。しかも、上述したように簡
易な回路構成で実現できる上、変調器１の変調機
能に悪影響を及ぼす虞れもない。特にパルス変調
器１の内部で温度補償を行うような従来の安定化
方式と異なるので、広範囲な補償を行い得る。そ
の上、基準レベル期間を利用して補償制御を行う
ので制御ループが極めて安定である等の絶大なる
効果を奏する。 As described above, according to the present device, it is possible to stabilize the modulation frequency with high precision through relatively simple control. Moreover, as described above, it can be realized with a simple circuit configuration, and there is no possibility that the modulation function of the modulator 1 will be adversely affected. In particular, since this is different from conventional stabilization methods in which temperature compensation is performed inside the pulse modulator 1, a wide range of compensation can be performed. Furthermore, since the compensation control is performed using the reference level period, great effects such as extremely stable control loops are achieved.
尚、本発明は上記実施例に限定されるものでは
ない。例えば基準レベル期間にのみ周波数比較を
行うように装置を構成することもできる。また前
述したように他のパルス変調方式であつても同様
に適用できることは云うまでもない。また誤差検
出および周波数誤差の保持等を全デイジタル的に
行うようにしても良いことは勿論のことである。
また誤差周波数の量、例えば周波数差を直接検出
してこの値に対応した補償値を帰還するように構
成することもできる。要するに本発明は、その要
旨を逸脱しない範囲で種種変形して実施すること
ができる。 Note that the present invention is not limited to the above embodiments. For example, the device may be configured to perform frequency comparison only during the reference level period. Furthermore, as mentioned above, it goes without saying that other pulse modulation methods can be similarly applied. It goes without saying that error detection, frequency error holding, etc. may be performed entirely digitally.
It is also possible to directly detect the amount of error frequency, for example, the frequency difference, and feed back a compensation value corresponding to this value. In short, the present invention can be implemented with various modifications without departing from the gist thereof.
図は本発明の一実施例を示すパルス変調器と周
波数安定化装置の概略構成図である。
１…パルス変調器、２…クランプ回路、３…加
算器、４…同期信号抽出回路、５，７…デユーテ
イ補正回路、６…基準周波数発振器、８…デイジ
タル位相比較器、９…スイツチ回路、１０…チヤ
ージポンプ回路、１１…コンデンサ、１２…低域
波器。
The figure is a schematic configuration diagram of a pulse modulator and a frequency stabilizing device showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Pulse modulator, 2...Clamp circuit, 3...Adder, 4...Synchronization signal extraction circuit, 5, 7...Duty correction circuit, 6...Reference frequency oscillator, 8...Digital phase comparator, 9...Switch circuit, 10 ...Charge pump circuit, 11...Capacitor, 12...Low frequency device.
Claims (1)
号の所定の周期毎に繰返される基準レベル期間を
検出する検出器と、この検出器で検出された前記
基準レベル期間に前記パルス変調器から出力され
るパルス変調信号の周波数と基準信号の周波数と
を比較してその周波数誤差を検出する誤差検出器
と、前記入力信号に比較して十分長い積分時定数
をもち、前記誤差検出器にて検出された周波数誤
差に対応する信号値を前記基準レベル期間毎に積
分し、その積分値を保持するチヤージポンプ回路
と、このチヤージポンプ回路に蓄えられた積分値
を前記入力信号に加算合成して前記パルス変調器
に与える帰還回路とを具備したことを特徴とする
パルス変調器の周波数安定化装置。 ２ 入力信号は画像信号であつて、検出器はこの
画像信号中の同期信号を抽出して基準レベル帰還
を検出するものである特許請求の範囲第１項に記
載のパルス変調器の周波数安定化装置。 ３ 入力信号に加算合成される積分値は、電圧値
として与えられるものである特許請求の範囲第１
項に記載のパルス変調器の周波数安定化装置。[Claims] 1. A detector that detects a reference level period that is repeated every predetermined cycle of an input signal that is pulse-modulated by a pulse modulator, and a detector that detects a reference level period that is repeated every predetermined period of an input signal that is pulse-modulated by a pulse modulator, and a an error detector that compares the frequency of the pulse modulated signal output from the device with the frequency of the reference signal and detects a frequency error therebetween; and the error detector has a sufficiently long integration time constant compared to the input signal. A charge pump circuit that integrates the signal value corresponding to the frequency error detected in each of the reference level periods and holds the integrated value; and a charge pump circuit that adds and synthesizes the integrated value stored in this charge pump circuit to the input signal. A frequency stabilizing device for a pulse modulator, comprising a feedback circuit that provides feedback to the pulse modulator. 2. Frequency stabilization of a pulse modulator according to claim 1, wherein the input signal is an image signal, and the detector extracts a synchronization signal from this image signal to detect reference level feedback. Device. 3. The integral value added and synthesized to the input signal is given as a voltage value.
A frequency stabilizing device for a pulse modulator according to paragraph 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18580680A JPS57109422A (en) | 1980-12-26 | 1980-12-26 | Frequency stabilizing device for pulse modulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18580680A JPS57109422A (en) | 1980-12-26 | 1980-12-26 | Frequency stabilizing device for pulse modulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57109422A JPS57109422A (en) | 1982-07-07 |
| JPH025050B2 true JPH025050B2 (en) | 1990-01-31 |
Family
ID=16177210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18580680A Granted JPS57109422A (en) | 1980-12-26 | 1980-12-26 | Frequency stabilizing device for pulse modulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57109422A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4415989A1 (en) * | 1994-05-06 | 1995-11-09 | Philips Patentverwaltung | Adjustment circuit for frequency modulator |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53134641U (en) * | 1977-03-30 | 1978-10-25 |
-
1980
- 1980-12-26 JP JP18580680A patent/JPS57109422A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57109422A (en) | 1982-07-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6236267B1 (en) | Linearization for power amplifiers using feed-forward and feedback control | |
| US7701305B2 (en) | Frequency jittering control for varying the switching frequency of a power supply | |
| EP2932280B1 (en) | Voltage and temperature compensated frequency converter and method | |
| JPS56136008A (en) | Pulse-width modulating and amplifying circuit | |
| JPH0444446B2 (en) | ||
| KR0154797B1 (en) | Pulse width modulation control circuit | |
| JPH0898512A (en) | Output voltage stabilizing circuit and voltage multiplier using it | |
| EP0498553A2 (en) | Adaptive control method for power converters | |
| US5150082A (en) | Center frequency calibration for DC coupled frequency modulation in a phase-locked loop | |
| US6078224A (en) | Frequency standard generator | |
| US10511296B2 (en) | System and method for modulation and demodulation | |
| JPH025050B2 (en) | ||
| US4345219A (en) | Frequency agile hold-sample-hold phase detector | |
| JPS5486256A (en) | Frequency control circuit | |
| US4507624A (en) | Voltage-to-frequency converters | |
| KR0145860B1 (en) | Frequency multiplier using d/a converter | |
| KR940011376B1 (en) | Carrier frequency automatic control circuit for vtr | |
| GB2595312A (en) | Time encoding modulator circuitry | |
| KR950010063B1 (en) | Auto gain control & clamping circuit of image signal | |
| SU1480089A1 (en) | Frequency-modulated signal shaper | |
| KR960015575B1 (en) | Circuit for generating fm carrier wave signal | |
| SU1035775A1 (en) | Frequency modulated oscillation shaper | |
| JPS58181144A (en) | Integrator | |
| SU1091143A1 (en) | Pulse d.c.voltage stabilizer | |
| JPS5467661A (en) | Switching regulator controller |