JPS57103531A - Memory controller - Google Patents

Memory controller

Info

Publication number
JPS57103531A
JPS57103531A JP55180074A JP18007480A JPS57103531A JP S57103531 A JPS57103531 A JP S57103531A JP 55180074 A JP55180074 A JP 55180074A JP 18007480 A JP18007480 A JP 18007480A JP S57103531 A JPS57103531 A JP S57103531A
Authority
JP
Japan
Prior art keywords
memory
delivered
writing
register
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55180074A
Other languages
Japanese (ja)
Inventor
Shigeo Kimuro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55180074A priority Critical patent/JPS57103531A/en
Publication of JPS57103531A publication Critical patent/JPS57103531A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To realize the application of a local memory with high efficiency, by holding the data read out of the local memory to a writing register and at the same time writing the output of the writing register into a main memory via a DMAC. CONSTITUTION:A read signal LMR of a local memory 7 is delivered from an MEMR terminal of a direct memory access controller (DMAC) 10. Then the reading data delivered from a terminal DOUT of the memory 7 is set to a writing register 60 via a writing gate 61 with the timing by which a write request signal WMM is delivered to a main memory 1. On the other hand, a signal WMM delivered from a terminal IOW of the DMAC10 is supplied also to an OR gate 17, and the output signal MMREQ is delivered to the memory 1 via a bus driver 20. Then the data held at the register 60 is written into the memory 1 via a bus driver 3 when the memory 1 is set in a ready state. And the data is transferred repetitively from the memory 7 to the memory 1 by a prescribed frequency.
JP55180074A 1980-12-19 1980-12-19 Memory controller Pending JPS57103531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55180074A JPS57103531A (en) 1980-12-19 1980-12-19 Memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55180074A JPS57103531A (en) 1980-12-19 1980-12-19 Memory controller

Publications (1)

Publication Number Publication Date
JPS57103531A true JPS57103531A (en) 1982-06-28

Family

ID=16076998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55180074A Pending JPS57103531A (en) 1980-12-19 1980-12-19 Memory controller

Country Status (1)

Country Link
JP (1) JPS57103531A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59139428A (en) * 1982-12-28 1984-08-10 Fujitsu Ltd Direct memory access system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59139428A (en) * 1982-12-28 1984-08-10 Fujitsu Ltd Direct memory access system

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